Electronics Forum | Sun Aug 24 08:57:56 EDT 2008 | davef
For an nate measurement method, look here http://www.ipc.org/4.0_Knowledge/4.1_Standards/test/2.4.22c.pdf For bare boards, look to IPC-6012, par. 3.4.4 For assemblies, look to IPC-A-610
Electronics Forum | Thu Oct 14 20:42:07 EDT 1999 | Jeff Ferry
Grace, As deifned in IPC 7721 Procedure 3.2 Bow and Twist Repair "Bow and twist after soldering shall not exceed 1.5% for through hole PC boards and .75% for surface mount PC boards. The bow and twist shall not be sufficient to cause difficulties d
Electronics Forum | Thu Aug 09 07:53:16 EDT 2012 | davef
Allowable bow & twist: Together, both IPC-A-600G and IPC-6012B represent the core IPC documents for describing the acceptable and nonconforming conditions that are either externally or internally visible on finished printed boards. IPC-A-600G relies
Electronics Forum | Mon Jan 23 03:12:13 EST 2006 | adeline_ko
The FA department is using IPC or J-STD-003 to do the solderability test for the leaded PCB FA qualification. Class A. However, there is no mention of Lead free testing for the PCB bare brd. Can anyone advise whether IPC has release a solderability
Electronics Forum | Mon Jan 23 20:58:08 EST 2006 | davef
J-STD-003B - Solderability Tests for Printed Boards is currently a "Working Draft". Look here: http://www.ipc.org/status.asp
Electronics Forum | Mon Mar 04 15:29:47 EST 2002 | genny
IPC-TM-650 is free downloadable test methods defined by IPC. Check their website. http://www.ipc.org, and look for the free downloads section. The manual is divided into several subcategories, and I believe under mechanical test methods there are
Electronics Forum | Thu Jan 02 11:35:30 EST 2003 | Richard
Cleanliness test � �Area Grid Arrays�. Evaluation of residues� resistivity in a specific location on the board. (As compared to �Solvent Extract� evaluation.) We are: SMT assembly, using standard �water soluble� process with micro BGAs (example: C
Electronics Forum | Mon Jun 19 09:54:21 EDT 2000 | Paul Houston
Go to www.ipc.org and click on search. search for: IPC Test Methods Manual Section 6 IPC TM-650 Test Methods Manual SECTION 2.6 - ENVIRONMENTAL TEST METHODS Paul
Electronics Forum | Mon Feb 23 14:44:08 EST 2009 | sunny
Are boards produced using Vapor phase ovens dirtier than N2 Reflow oven. Are there any studies/papers someone can point to? if not what are the methods to verify this? is IPC specified SIR test using 24B SIR test coupons? please advise. thanks in adv
Electronics Forum | Sun Jun 07 19:09:21 EDT 1998 | Graham Naisbitt
Chiakl Ion Chromatography has been perfectly described by Dave, but here are a couple of extra considerations: Ion Chromatography will tell you precisely what is present on the surface of your board/assembly but it will not tell you whether it will b
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