Electronics Forum | Wed Apr 27 11:43:32 EDT 2005 | patrickbruneel
Hi Daan, What we did in the time was pareto analyses on all board designs to determine the critical areas (mainly design errors) and only inspect those specific problem areas. Every batch had a copy of the PC board with problem areas marked and only
Electronics Forum | Thu Oct 02 12:22:26 EDT 2008 | JerryS
Hello Ok there is not much info here. What you have to mae sure of is several key factors. 1. Have you entered the correct stencil thickness. 2. Are you using the stencil gerber (not the paste layer) The paste layer is usually not adjusted for ap
Electronics Forum | Wed May 20 17:00:56 EDT 2009 | dyoungquist
We just placed a 56 pin QFN, 1 per board, on 10 boards and had zero defects. A good paste job, proper placement and a correct oven profile are the keys. If these are set up correctly, on larger runs your defects won't be zero but they should be le
Electronics Forum | Tue Sep 18 11:34:36 EDT 2001 | jschake
The tightest spacing between neighboring 0201 components assembled was 8-mils. Please refer to the response for the query entitled �Minimizing Tombstoning Defects� posted by martys, as the response provided there is also relevant to address this que
Electronics Forum | Mon Mar 03 13:18:02 EST 2003 | msivigny
Hello phil, The use of AOI systems give us the opportunity to auto-collect defect information much the way you're using them now. AOI systems become extremely effective when the collected data is used to perform some positive change into the process.
Electronics Forum | Tue Jun 05 14:38:55 EDT 2001 | pteerink
You would be better served to check your print quality as you run. Any problems caused by dirty stencils ( plugged aps etc ) would show up right away as a defect. Search the forum for more on this subject. I seem to recall the same subject coming up
Electronics Forum | Wed Mar 05 03:43:58 EST 2003 | testing
Hi, Mike Thanks for the reply With your oracle system were you able to perfom SPC analysis? and if possible do you have any Material that may be helpful for me to get my system setup i.e. whether through Excel, Access, Oracle etc. + What are your
Electronics Forum | Wed Mar 02 18:46:02 EST 2005 | Austinj
The tendancy always has been "when in doubt, touch it up"... this is not the way to "verify the process" and is not the best strategy for multiple reasons (unessecary rework, additional labor costs, as well as making the solder joint more brittle, [i
Electronics Forum | Tue Nov 11 17:35:08 EST 2008 | davef
SM-840, is a material qualification document only, with all the test requirements applicable only to a defined test coupon, not to production boards. So, it's useless for what you're trying to accomplish. As assemblers use A-610 - Acceptability Of E
Electronics Forum | Sun Aug 26 12:40:59 EDT 2001 | stefwitt
I would like to enter the discussion by tossing some numbers in. First of all I don�t like the 3 Sigma value. 3 Sigma are 2000 defects per mio. if I remember correctly. This means, if you have 200 components on the board, then every 10 boards have on
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