Technical Library | 2014-09-11 11:36:46.0
There are a variety of methods one can use to rework QFNs. This paper explains one of the ways to get very little center ground voiding while making it easy to place a tiny component with almost no keep out areas.
Technical Library | 1999-08-09 11:36:27.0
Shrinking process technologies and increasing design sizes continually challenge design methodologies and EDA tools to develop at an ever-increasing rate. Before the complexities of deep submicron (DSM), gate and transistor delays dominated interconnect delays, and enabled simplified design methodologies that could focus on device analysis. The advent of DSM processes is changing all of this, invalidating assumptions and approximations that existing design methodologies are based upon, and forcing design teams to re-tool. High-capacity parasitic extraction tools are now critical for successful design tape-outs.
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