Technical Library | 2013-09-19 17:25:32.0
The next generation of smart phones will demand very thin multi-layer boards to reduce the product thickness again. This paper shows three different manufacturing approaches, which can be used for very thin any-layer build-ups. The technological approaches are compared on reliability level – the any-layer copper filled micro-via technology which is to be considered as state of the art technology for high end phones and the ALIVH-C/G technology that is well established in Japan. A test vehicle design featuring test coupons for comprehensive reliability test series has been defined as target application for investigation...
Technical Library | 2018-05-09 22:15:29.0
Creep corrosion on printed circuit boards (PCBs) is the corrosion of copper metallization and the spreading of the copper corrosion products across the PCB surfaces to the extent that they may electrically short circuit neighboring features on the PCB. The iNEMI technical subcommittee on creep corrosion has developed a flowers-of-sulfur (FOS) based test that is sufficiently well developed for consideration as an industry standard qualification test for creep corrosion. This paper will address the important question of how relative humidity affects creep corrosion. A creep corrosion tendency that is inversely proportional to relative humidity may allow data center administrators to eliminate creep corrosion simply by controlling the relative humidity in the data center,thus, avoiding the high cost of gas-phase filtration of gaseous contamination. The creep corrosion relative humidity dependence will be studied using a modified version of the iNEMI FOS test chamber. The design modification allows the achievement of relative humidity as low as 15% in the presence of the chlorine-releasing bleach aqueous solution. The paper will report on the dependence of creep corrosion on humidity in the 15 to 80% relative humidity range by testing ENIG (gold on electroless nickel), ImAg (immersion silver) and OSP (organic surface preservative) finished PCBs, soldered with organic acid flux.
Technical Library | 2023-07-16 21:56:12.0
Imagine being able to accurately predict the correct artwork compensations prior to taking on a large quick turn order regardless of the board design, materials, or process. Such predictive power is possible and can be achieved without a lot of cost and complexity. This paper shows how small sets of designed experiments can be used to create a cImagine being able to accurately predict the correct artwork compensations prior to taking on a large quick turn order regardless of the board design, materials, or process. Such predictive power is possible and can be achieved without a lot of cost and complexity. This paper shows how small sets of designed experiments can be used to create a compensation model. Before a discussion of the design of experiments (DOEs), we will examine key processes and material variables that affect movement as demonstrated on real board design layout in a real production process. Only the few most relevant variables need to be included in the experimental design. A solution is presented that uses small experiments that provide the required information for constructing a general compensation model.mpensation model. Before a discussion of the design of experiments (DOEs), we will examine key processes and material variables that affect movement as demonstrated on real board design layout in a real production process. Only the few most relevant variables need to be included in the experimental design. A solution is presented that uses small experiments that provide the required information for constructing a general compensation model.
Technical Library | 2021-07-20 20:02:29.0
During the manufacturing of printed circuit boards (PCBs) for a Flight Project, it was found that a European manufacturer was building its boards to a European standard that had no requirement for copper wrap on the vias. The amount of copper wrap that was measured on coupons from the panel containing the boards of interest was less than the amount specified in IPC-6012 Rev B, Class 3. To help determine the reliability and usability of the boards, three sets of tests and a simulation were run. The test results, along with results of simulation and destructive physical analysis, are presented in this paper. The first experiment involved subjecting coupons from the panels supplied by the European manufacturer to thermal cycling. After 17 000 cycles, the test was stopped with no failures. A second set of accelerated tests involved comparing the thermal fatigue life of test samples made from FR4 and polyimide with varying amounts of copper wrap. Again, the testing did not reveal any failures. The third test involved using interconnect stress test coupons with through-hole vias and blind vias that were subjected to elevated temperatures to accelerate fatigue failures. While there were failures, as expected, the failures were at barrel cracks. In addition to the experiments, this paper also discusses the results of finite-element analysis using simulation software that was used to model plated-through holes under thermal stress using a steady-state analysis, also showing the main failure mode was barrel cracking. The tests show that although copper wrap was sought as a better alternative to butt joints between barrel plating and copper foil layers, manufacturability remains challenging and attempts to meet the requirements often result in features that reduce the reliability of the boards. Experimental and simulation work discussed in this paper indicate that the standard requirements for copper wrap are not contributing to the overall board reliability, although it should be added that a design with a butt joint is going to be a higher risk than a reduced copper wrap design. The study further shows that procurement requirements for wrap plating thickness from Class 3 to Class 2 would pose little risk to reliability (minimum 5 μm/0.197 mil for all via types).Experimental results corroborated by modeling indicate that the stress maxima are internal to the barrels rather than at the wrap location. In fact, the existence of Cu wrap was determined to have no appreciable effect on reliability.
Technical Library | 2021-06-21 19:34:02.0
In this era of electronics miniaturization, high yield and low-cost integrated circuit (IC) substrates play a crucial role by providing a reliable method of high density interconnection of chip to board. In order to maximize substrate real-estate, the distance between Cu traces also known as line and space (L/S) should be minimized. Typical PCB technology consists of L/S larger than 40 µ whereas more advanced wafer level technology currently sits at or around 2 µm L/S. In the past decade, the chip size has decreased significantly along with the L/S on the substrate. The decreasing chip scales and smaller L/S distances has created unique challenges for both printed circuit board (PCB) industry and the semiconductor industry. Fan-out panel-level packaging (FOPLP) is a new manufacturing technology that seeks to bring the PCB world and IC/semiconductor world even closer. While FOPLP is still an emerging technology, the amount of high-volume production in this market space provide a financial incentive to develop innovative solutions in order to enable its ramp up. The most important performance aspect of the fine line plating in this market space is plating uniformity or planarity. Plating uniformity, trace/via top planarity, which measures how flat the top of the traces and vias are a few major features. This is especially important in multilayer processing, as nonuniformity on a lower layer can be transferred to successive layers, disrupting the device design with catastrophic consequences such as short circuits. Additionally, a non-planar surface could also result in signal transmission loss by distortion of the connecting points, like vias and traces. Therefore, plating solutions that provide a uniform, planar profile without any special post treatment are quite desirable.
Technical Library | 2021-06-07 19:06:32.0
The technological growth of the last decades has brought many improvements in daily life, but also concerns on how to deal with electronic waste. Electrical and electronic equipment waste is the fastest-growing rate in the industrialized world. One of the elements of electronic equipment is the printed circuit board (PCB) and almost every electronic equipment has a PCB inside it. While waste PCB (WPCB) recycling may result in the recovery of potentially precious materials and the reuse of some components, it is a challenging task because its composition diversity requires a cautious pre-processing stage to achieve optimal recycling outcomes. Our research focused on proposing a method to evaluate the economic feasibility of recycling integrated circuits (ICs) from WPCB. The proposed method can help decide whether to dismantle a separate WPCB before the physical or mechanical recycling process and consists of estimating the IC area from a WPCB, calculating the IC's weight using surface density, and estimating how much metal can be recovered by recycling those ICs. To estimate the IC area in a WPCB, we used a state-of-the-art object detection deep learning model (YOLO) and the PCB DSLR image dataset to detect the WPCB's ICs. Regarding IC detection, the best result was obtained with the partitioned analysis of each image through a sliding window, thus creating new images of smaller dimensions, reaching 86.77% mAP. As a final result, we estimate that the Deep PCB Dataset has a total of 1079.18 g of ICs, from which it would be possible to recover at least 909.94 g of metals and silicon elements from all WPCBs' ICs. Since there is a high variability in the compositions of WPCBs, it is possible to calculate the gross income for each WPCB and use it as a decision criterion for the type of pre-processing.
Technical Library | 2019-09-24 15:41:53.0
This paper focuses on three different coating material groups which were formulated to operate under high thermal stress and are applied at printed circuit board manufacturing level. While used for principally different applications, these coatings have in common that they can be key to a successful thermal management concept especially in e-mobility and lighting applications. The coatings consist of: Specialty (green transparent) liquid photoimageable solder masks (LPiSM) compatible with long-term thermal storage/stress in excess of 150°C. Combined with the appropriate high-temperature base material, and along with a suitable copper pre-treatment, these solder resists are capable of fulfilling higher thermal demands. In this context, long-term storage tests as well as temperature cycling tests were conducted. Moreover, the effect of various Cu pre-treatment methods on the adhesion of the solder masks was examined following 150, 175 and 200°C ageing processes. For this purpose, test panels were conditioned for 2000 hours at the respective temperatures and were submitted to a cross-cut test every 500 h. Within this test set-up, it was found that a multi-level chemical pre-treatment gives significantly better adhesion results, in particular at 175°C and 200°C, compared with a pre-treatment by brush or pumice brush. Also, breakdown voltage as well as tracking resistance were investigated. For an application in LED technology, the light reflectivity and white colour stability of the printed circuit board are of major importance, especially when high-power LEDs are used which can generate larger amounts of heat. For this reason, a very high coverage power and an intense white colour with high reflectivity values are essential for white solder masks. These "ultra-white" and largely non-yellowing LPiSM need to be able to withstand specific thermal loads, especially in combination with high-power LED lighting applications. The topic of thermal performance of coatings for electronics will also be discussed in view of printed heatsink paste (HSP) and thermal interface paste (TIP) coatings which are used for a growing number of applications. They are processed at the printed circuit board manufacturing level for thermal-coupling and heat-spreading purposes in various thermal management-sensitive fields, especially in the automotive and LED lighting industries. Besides giving an overview of the principle functionality, it will be discussed what makes these ceramic-filled epoxy- or silicone-based materials special compared to using "thermal greases" and "thermal pads" for heat dissipation purposes.
Technical Library | 2014-08-14 17:58:41.0
High reliability applications for high performance computing, military, medical and industrial applications are driving electronics packaging advancements toward increased functionality with decreasing degrees of size, weight and power (SWaP) The substrate technology selected for the electronics package is a key enabling technology towards achieving SWaP. Standard printed circuit boards (PWBs) utilize dielectric materials containing glass cloth, which can limit circuit density and performance, as well as inhibit the ability to achieve reliable assemblies with bare semiconductor die components. Ceramic substrates often used in lieu of PWBs for chip packaging have disadvantages of weight, marginal electrical performance and reliability as compared to organic technologies. Alternative materials including thin, particle-containing organic substrates, liquid crystal polymer (LCP) and microflex enable SWaP, while overcoming the limitations of PWBs and ceramic. This paper will discuss the use of these alternative organic substrate materials to achieve extreme electronics miniaturization with outstanding electrical performance and high reliability. The effect of substrate type on chip-package interaction and resulting reliability will be discussed. Microflex assemblies to achieve extreme miniaturization and atypical form factors driven by implantable and in vivo medical applications are also shown.
Technical Library | 2016-10-20 18:13:34.0
Pad cratering failure has emerged due to the transition from traditional SnPb to SnAgCu alloys in soldering of printed circuit assemblies. Pb-free-compatible laminate materials in the printed circuit board tend to fracture under ball grid array pads when subjected to high strain mechanical loads. In this study, two Pb-free-compatible laminates were tested, plus one dicycure non-Pb-free-compatible as control. One set of these samples were as-received and another was subjected to five reflows. It is assumed that mechanical properties of different materials have an influence on the susceptibility of laminates to fracture. However, the pad cratering phenomenon occurs at the layer of resin between the exterior copper and the first glass in the weave. Bulk mechanical properties have not been a good indicator of pad crater susceptibility. In this study, mechanical characterization of hardness and Young’s modulus was carried out in the critical area where pad cratering occurs using nano-indentation at the surface and in a cross-section. The measurements show higher modulus and hardness in the Pb-free compatible laminates than in the dicy-cured laminate. Few changes are seen after reflow – which is known to have an effect -- indicating that these properties do not provide a complete prediction. Measurements of the copper pad showed significant material property changes after reflow.
Technical Library | 2024-07-24 00:51:44.0
A blade server system (BSS) utilizes voltage regulator modules (VRMs), in the form of quad flat no-lead (QFN) devices, to provide power distribution to various components on the system board. Depending on the power requirements of the circuit, these VRMs can be mounted as single devices or banked together. In addition, the power density of the VRM can be high enough to warrant heat dissipation through the use of a heat sink. Typically, at field conditions (FCs), the BSS are powered on and off up to four times per day, with their ambient temperature cycling between 258C and 808C. This cyclical temperature gradient drives inelastic strain in the solder joints due to the coefficient of thermal expansion (CTE) mismatch between the QFN and the circuit card. In addition, the heat sink, coupled with the QFN and the circuit card, can induce additional inelastic solder joint strain, resulting in early solder joint fatigue failure. To understand the effect of the heat sink mounting, a FEM (finite element model of four QFNs mounted to a BSS circuit card was developed. The model was exercised to calculate the maximum strain energy in a critical joint due to cyclic strain, and the results were compared for a QFN with and without a heat sink. It was determined that the presence of the heat sink did contribute to higher strain energy and therefore could lead to earlier joint failure. Although the presence of the heat sink is required, careful design of the mounting should be employed to provide lateral slip, essentially decoupling the heat sink from the QFN joint strain. Details of the modeling and results, along with DIC (digital image correlation) measurements of heat sink lateral slip, are presented.
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