Technical Library | 2012-12-17 22:05:22.0
Package on Package (PoP) has become a relatively common component being used in mobile electronics as it allows for saving space in the board layout due to the 3D package layout. To insure device reliability through drop tests and thermal cycling as well as for protecting proprietary programming of the device either one or both interconnect layers are typically underfilled. When underfill is applied to a PoP, or any component for that matter, there is a requirement that the board layout is such that there is room for an underfill reservoir so that the underfill material does not come in contact with surrounding components. The preferred method to dispensing the underfill material is through a jetting process that minimizes the wet out area of the fluid reservoir compared to traditional needle dispensing. To further minimize the wet out area multiple passes are used so that the material required to underfill the component is not dispensed at once requiring a greater wet out area. Dispensing the underfill material in multiple passes is an effective way to reduce the wet out area and decrease the distance that surrounding components can be placed, however, this comes with a process compromise of additional processing time in the underfill dispenser. The purpose of this paper is to provide insight to the inverse relationship that exists between the wet out area of the underfill reservoir and the production time for the underfill process.
Technical Library | 2013-03-21 21:24:49.0
This paper explores the behaviour of a copper test vehicle with multiple reflowed solder joints, which has direct relevance to ball grid arrays (BGA) and high density interconnect structures. The paper explores the relative stress conditions on the distributed joints and the sensitivity to ball joint shape... First published in the 2012 IPC APEX EXPO technical conference proceedings
Technical Library | 2012-12-27 14:35:29.0
Printed Electronics is generally defined as the patterning of electronic materials, in solution form, onto flexible substrates, omitting any use of the photolithography, etching, and plating steps commonly found within the Printed Circuit Board (PCB) industry. The origins of printed electronics go back to the 1960s, and close variants of several original applications and market segments remain active today. Through the 1980s and 1990s Printed Electronic applications based on Membrane Touch Switch and Electroluminescent lighting technologies became common, and the screen printed electronic materials used then have formed the building blocks for many of the current and emerging technologies and applications... First published in the 2012 IPC APEX EXPO technical conference proceedings.
Technical Library | 2012-12-13 21:20:05.0
First published in the 2012 IPC APEX EXPO technical conference proceedings. We investigated the micro-void formation of solder joints after reliability tests such as preconditioning (precon) and thermal cycle (TC) by varying the thickness of Palladium (Pd) in Electroless Nickel / Electroless Palladium / Immersion Gold (ENEPIG) surface finish. We used lead-free solder of Sn-1.2Ag-0.5Cu-Ni (LF35). We found multiple micro-voids of less than 10 µm line up within or above the intermetallic compound (IMC) layer. The number of micro-voids increased with the palladium (Pd) layer thickness. Our results revealed that the micro-void formation should be related to (Pd, Ni)Sn4 phase resulted from thick Pd layer. We propose that micro-voids may form due to either entrapping of volatile gas by (Pd, Ni)Sn4 or creeping of (Pd, Ni)Sn4.
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