Technical Library: 20x 2012 2013 (Page 1 of 2)

Existing and Emerging Opportunities in Printed Electronics For Printers

Technical Library | 2013-05-02 12:45:25.0

Summary of some new and existing technologies for printed electronics outside of traditional membrane switch manufacturing. Discussion of requirements for understanding the technology of these applications in order to capitalize on them... First published in the 2012 IPC APEX EXPO technical conference proceedings.

Conductive Compounds, Inc.

Projection Moiré vs. Shadow Moiré for Warpage Measurement and Failure Analysis of Advanced Packages

Technical Library | 2013-01-31 18:43:15.0

There are three key industry trends that are driving the need for temperature-dependent warpage measurement: the trend toward finer-pitch devices, the emergence of lead-free processing, and changes in device form factors. Warpage measurement has become a key measurement for analysis; prevention and prediction of interconnect defects and has been employed in failure analysis labs and production sites worldwide. First published in the 2012 IPC APEX EXPO technical conference proceedings

ZN Technologies

Low Cycle Fatigue Behaviour of Multi-joint Sample in Mechanical Testing

Technical Library | 2013-03-21 21:24:49.0

This paper explores the behaviour of a copper test vehicle with multiple reflowed solder joints, which has direct relevance to ball grid arrays (BGA) and high density interconnect structures. The paper explores the relative stress conditions on the distributed joints and the sensitivity to ball joint shape... First published in the 2012 IPC APEX EXPO technical conference proceedings

National Physical Laboratory

No-Clean Flux Residue and Underfill Compatibility Effects on Electrical Reliability

Technical Library | 2013-04-11 15:43:17.0

With the explosion of growth in handheld electronics devices, manufacturers have been forced to look for ways to reinforce their assemblies against the inevitable bumps and drops that their products experience in the field. One method of reinforcement has been the utilization of underfills to "glue" certain SMDs to the PCB. Bumped SMDs attached to the PCB with a no-clean soldering process offer the unavoidable scenario of the underfill coming in contact with a flux residue. This may or may not create a reliability issue... First published in the 2012 IPC APEX EXPO technical conference proceedings

Indium Corporation

Determination of Copper Foil Surface Roughness from Micro-section Photographs

Technical Library | 2013-04-25 11:42:01.0

Specification and control of surface roughness of copper conductors within printed circuit boards (PCBs) are increasingly desirable in multi-GHz designs as a part of signal-integrity failure analysis on high-speed PCBs. The development of a quality-assurance method to verify the use of foils with specified roughness grade during the PCB manufacturing process is also important... First published in the 2012 IPC APEX EXPO technical conference proceedings.

Cisco Systems, Inc.

Impact of Dust on Printed Circuit Assembly Reliability

Technical Library | 2013-05-09 14:35:18.0

Atmospheric dust consists of solids suspended in air. Dust is well known for its complex nature. It normally includes inorganic mineral materials, water soluble salts, organic materials, and a small amount of water. The impact of dust on the reliability of printed circuit board assemblies (PCBAs) is ever-growing, driven by the miniaturization of technology and the increasing un-controlled operating conditions with more dust exposure in telecom and information industries... First published in the 2012 IPC APEX EXPO technical conference proceedings.

CALCE Center for Advanced Life Cycle Engineering

IPC Standards and Printed Electronics Monetization

Technical Library | 2013-05-23 17:41:21.0

Printed Electronics is considered by many international technologists to be a platform for manufacturing innovation. Its rich portfolio of advanced multi-functional nano-designed materials, scalable ambient processes, and high volume manufacturing technologies lends itself to offer an opportunity for sustained manufacturing innovation. The success of introducing a new manufacturing technology is strongly dependent on the ability to achieve high final product yields at current or reduced cost. In the past, standards have been the critical vehicles to enable manufacturing success... First published in the 2012 IPC APEX EXPO technical conference proceedings.

Printovate Technologies, Inc.

PTH Core-to-Core Interconnect Using Sintered Conductive Pastes

Technical Library | 2013-03-07 18:25:36.0

The market for high-layer-count printed circuit boards (PCB) containing blind and buried vias was once relatively small, and focused on specialized applications in the military and high end computing. The demand for these types of PCBs today is being driven by an increasing number of commercial applications in the telecommunications and semiconductor test market segments. These applications typically require high-aspect-ratio plated-through-holes (PTHs) and blind and buried vias in order to meet the applications interconnect density requirements. Blind and buried vias and high aspect ratio PTHs continue to present manufacturing challenges and frequently are the limiting features to achieving high fabrication yield... First published in the 2012 IPC APEX EXPO technical conference proceedings

Ormet Circuits, Inc.

IPC 9252A Electrical Test Considerations & Military Specifications versus Electrical Test

Technical Library | 2013-04-04 15:28:39.0

This paper will outline and define what requirements must be adhered to for the OEM community to truly achieve the IPC class product from the Electrical Test standpoint. This will include the test point optimization matrix, Isolation (shorts) parameters and Continuity (opens) parameters. This paper will also address the IPC Class III/A additional requirements for Aerospace and Military Avionics. The disconnect exists between OEMs understanding the requirements of their specific IPC class design versus the signature that will be presented from their design. This results in many Class III builds failing at Electrical Test... First published in the 2012 IPC APEX EXPO technical conference proceedings

Gardien Services USA

Boundary Scan Advanced Diagnostic Methods

Technical Library | 2013-02-14 12:54:29.0

Boundary-scan (1149.1) technology was originally developed to provide a far easier method to perform digital DC testing to detect intra-IC interconnect assembly faults, such as solder shorts and opens. Today's advanced IC technology now includes high-speed differential interfaces that include AC or DC coupling components loaded on the printed circuit assembly. Simple stuck-at-high/low test methods are not sufficient to detect all assembly fault conditions, which includes shorts, opens and missing components. Improved diagnostics requires detailed circuit analysis, predictive assembly fault simulation and more complex testing to isolate and accurately detect all possible assembly faults... First published in the 2012 IPC APEX EXPO technical conference proceedings

Agilent Technologies, Inc.

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