Technical Library: 24vac and 2009 (Page 1 of 1)

A Compliant and Creep Resistant SAC-Al(Ni) Alloy

Technical Library | 2009-03-27 22:22:40.0

The Sn-Ag-Cu (SAC) alloys have been considered promising replacements for the lead-containing solders for the microelectronics applications. However, due to the rigidity of the SAC alloys, compared with the Pb-containing alloys, more failures have been found in the drop and high impact applications for the portable electronic devices, such as the personal data assistant (PDA), cellular phone, notebook computer..etc

Indium Corporation

Screen and Stencil Printing Processes for Wafer Backside Coating

Technical Library | 2009-09-09 15:08:19.0

Stencil printing equipment has traditionally been used in the surface mount assembly industry for solder paste printing. In recent years the flexibility of the tool has been exploited for a wide range of materials and processes to aid semiconductor packaging and assembly. One such application has been the deposition of adhesive coatings onto the backside of silicon wafers.

ASM Assembly Systems (DEK)

Effects of an Appropriate PCB Layout and Soldering Nozzle Design on Quality and Cost Structure in Selective Soldering Processes

Technical Library | 2009-10-29 11:45:52.0

The globalization of markets results in stronger competition with clearly noticeably cost pressure. For companies producing electronic equipment it is therefore of existential importance to reduce production costs whilst maintaining a consistently high quality level of the manufactured products. Manual repair soldering that is expensive, time-consuming and cost intensive is already unacceptable due to the required quality and the reproducibility of the whole manufacturing process.

SEHO Systems GmbH

SnCu Based Alloy Design for Lower Copper Dissolution and Better Process Control

Technical Library | 2009-02-13 12:29:39.0

To meet the market demand for a best-in-class, low-cost leadfree alloy for wave, selective and dip soldering

Kester

Solder Phase Coarsening, Fundamentals, Preparation, Measurement and Prediction

Technical Library | 2009-05-07 23:23:00.0

Thermal fatigue has been one of the most serious problems for solder joint reliability. Thermo-mechanical fatigue failure is considered to be closely related to micro-structural coarsening (grain/phase growth). Factors that influence the phase growth are studied and measurement methods are discussed, including the preparation of the eutectic solder sample for phase size measurement. Three categories of models used to predict grain growth in polycrystalline materials are presented. Finally, phase growth in solder during high temperature aging and temperature cycling and its use as a damage correlation factor are discussed.

DfR Solutions (acquired by ANSYS Inc)

SMT Placement for ICs, Connectors and Odd-Shaped Components

Technical Library | 2009-11-18 23:37:52.0

Accurate component placement is a basic requirement for any pick and place machine. The first step towards accurate placement is accurate centering, or measurement of the component’s position on the placement head. One of the most widely used centering methods for ICs, connectors, and odd‐shaped components are a camera based system that measures the component position relative to a known point. Camera based centering systems include three main elements: lighting, camera, and software. Each of these elements are critical to obtaining an accurate measurement of the component and ultimately for accurate component placement on the PCB. As the old adage goes, the system is only as strong as its weakest link.

Juki Automation Systems

An Experimental and Computational Study of the Current Carrying Capacity of High Performance PWB Interconnections

Technical Library | 2009-01-01 16:37:38.0

Recent technology advancement has enabled enhancement in PWB electrical performance and wiring density. These innovations have taken the form of improved materials, novel PWB interconnect structures, and manufacturing technology. One such advancement is Z-axis conductive interconnect. The Z-interconnect technology involves building mini-substrates of 2 or 3 layers each, then assembling several mini-substrates together using conductive paste.

i3 Electronics

Reliability and Failure Mechanisms of Laminate Substrates in a Pb-free World

Technical Library | 2009-04-30 18:06:24.0

This presentation surveys the most significant via and via-related laminate failure mechanisms from past to present using data from current induced thermal cycling (CITC) testing, failure analysis, and other sources. The relative life and failure modes of thru vias, buried vias, and microvias (stacked vs. non-stacked) are compared, along with the affect of structure, materials, and peak temperatures on the above. The origin of via-induced laminate failures such as "eyebrow cracks" and Pb free related internal delamination is also explored.

i3 Electronics

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