Technical Library | 2020-07-22 19:39:05.0
The PWB industry needs to complete reliability testing in order to define the minimum copper wrap plating thickness requirement for confirming the reliability of PTH structures. Predicting reliability must ensure that the failure mechanism is demonstrated as a wear-out failure mode because a plating wrap failure is unpredictable. The purpose of this study was to quantify the effects of various copper wrap plating thicknesses through IST testing followed by micro sectioning to determine the failure mechanism and identify the minimum copper wrap thickness required for a reliable PWB. Minimum copper wrap plating thickness has become an even a bigger concern since designers started designing HDI products with buried vias, microvias and through filled vias all in one design. PWBs go through multiple plating cycles requiring planarization after each plating cycle to keep the surface copper to a manageable thickness for etching. The companies started a project to study the relationship between Copper wrap plating thickness and via reliability. The project had two phases. This paper will present findings from both Phase 1 and Phase 2.
Technical Library | 2019-07-17 17:56:34.0
The increased demand for electronic devices in recent years has led to an extensive research in the field to meet the requirements of the industry. Electrolytic copper has been an important technology in the fabrication of PCBs and semiconductors. Aqueous sulfuric acid baths are explored for filling or building up with copper structures like blind micro vias (BMV), trenches, through holes (TH), and pillar bumps. As circuit miniaturization continues, developing a process that simultaneously fills vias and plates TH with various sizes and aspect ratios, while minimizing the surface copper thickness is critical. Filling BMV and plating TH at the same time, presents great difficulties for the PCB manufactures. The conventional copper plating processes that provide good via fill and leveling of the deposit tend to worsen the throwing power (TP) of the electroplating bath. TP is defined as the ratio of the deposit copper thickness in the center of the through hole to its thickness at the surface. In this paper an optimization of recently developed innovative, one step acid copper plating technology for filling vias with a minimal surface thickness and plating through holes is presented.
Technical Library | 2017-11-22 12:38:51.0
The use of copper foils laminated to polyimide (PI) as flexible printed circuit board precursor is a standard practice in the PCB industry. We have previously described[1] an approach to very thin copper laminates of coating uniform layers of nano copper inks and converting them into conductive foils via photonic sintering with a multibulb conveyor system, which is consistent with roll-to-roll manufacturing. The copper thickness of these foils can be augmented by electroplating. Very thin copper layers enable etching fine lines in the flexible circuit. These films must adhere tenaciously to the polyimide substrate.In this paper, we investigate the factors which improve and inhibit adhesion. It was found that the ink composition, photonic sintering conditions, substrate pretreatment, and the inclusion of layers (metal and organic) intermediate between the copper and the polyimide are important.
Technical Library | 2020-09-02 22:14:36.0
The demand for miniaturization and higher density electronic products has continued steadily for years, and this trend is expected to continue, according to various semiconductor technology and applications roadmaps. The printed circuit board (PCB) must support this trend as the central interconnection of the system. There are several options for fine line circuitry. A typical fine line circuit PCB product using copper foil technology, such as the modified semi-additive process (mSAP), uses a thin base copper layer made by pre-etching. The ultrathin copper foil process (SAP with ultrathin copper foil) is facing a technology limit for the miniaturization due to copper roughness and thickness control. The SAP process using sputtered copper is a solution, but the sputtering process is expensive and has issues with via plating. SAP using electroless copper deposition is another solution, but the process involved is challenged to achieve adequate adhesion and insulation between fine-pitch circuitries. A novel catalyst system--liquid metal ink (LMI)--has been developed that avoids these concerns and promotes a very controlled copper thickness over the substrate, targeting next generation high density interconnect (HDI) to wafer-level packaging substrates and enabling 5-micron level feature sizes. This novel catalyst has a unique feature, high density, and atomic-level deposition. Whereas conventional tin-palladium catalyst systems provide sporadic coverage over the substrate surface, the deposited catalyst covers the entire substrate surface. As a result, the catalyst enables improved uniformity of the copper deposition starting from the initial stage while providing higher adhesion and higher insulation resistance compared to the traditional catalysts used in SAP processes. This article discusses this new catalyst process, which both proposes a typical SAP process using the new catalyst and demonstrates the reliability improvements through a comparison between a new SAP PCB process and a conventional SAP PCB process.
Technical Library | 2014-11-13 19:23:50.0
With increasing power loss of electrical components, thermal performance of an assembled device becomes one of the most important quality factors in electronic packaging. Due to the rapid advances in semiconductor technology, particularly in the regime of high-power components, the temperature dependence of the long-term reliability is a critical parameter and has to be considered with highest possible care during the design phase (...) The aim of this paper is to give a short overview about standard thermal solutions like thick copper, thermal vias, plugged vias or metal core based PCBs. Furthermore, attention will be turned on the development of copper filled thermal vias in thin board constructions...
Technical Library | 2017-06-13 17:14:59.0
For tin-rich solder alloys, 200 C (392 F) is an extreme temperature. Intermetallic growth in tin-copper systems is known to occur and is believed to bear a direct relationship to failure mechanisms. This study of morphological changes with time at elevated temperatures was made to determine growth rates of tin-copper intermetallics. Preferred growth directions, rates of thickening, and notable changes in morphology were observed.Each of four tin-base alloys was flowed on copper and exposed to temperatures between 100 C and 200 C for time periods of up to 32 days. Metallographic sections were taken and the intermetallics were examined. Intermetallic layer thickening is characterized by several distinct stages. The initial growth of side plates is extremely rapid and exaggerated. This is followed by retrogression (spheroidization) of the elongated peaks and by general thick-
Technical Library | 2016-07-21 18:16:06.0
Achieving optimum high-frequency printed-circuit-board (PCB) performance is not simply a matter of specifying the best possible PCB material, but can be significantly impacted by PCB fabrication practices. In addition to appropriate circuit materials and circuit design configurations to meet target performance goals, a number of PCB material-related issues can affect final performance, including the use of soldermask, the PCB copper plating thickness, the conductor trapezoidal effect, and plating finish; understanding the effects of these material issues can help when fabricating high-frequency circuits for the best possible electrical performance.
Technical Library | 2013-09-19 17:25:32.0
The next generation of smart phones will demand very thin multi-layer boards to reduce the product thickness again. This paper shows three different manufacturing approaches, which can be used for very thin any-layer build-ups. The technological approaches are compared on reliability level – the any-layer copper filled micro-via technology which is to be considered as state of the art technology for high end phones and the ALIVH-C/G technology that is well established in Japan. A test vehicle design featuring test coupons for comprehensive reliability test series has been defined as target application for investigation...
Technical Library | 2019-06-20 00:09:49.0
It is well known that during service the layer of Cu6Sn5 intermetallic at the interface between the solder and a Cu substrate grows but the usual concern has been that if this layer gets too thick it will be the brittleness of this intermetallic that will compromise the reliability of the joint, particularly in impact loading. There is another level of concern when the Cu-rich Cu3Sn phase starts to develop at the Cu6Sn5/Cu interface and an imbalance in the diffusion of atomic species, Sn and Cu, across that interface results in the formation at the Cu3Sn/Cu interface of Kirkendall voids, which can also compromise reliability in impact loading. However, when, as is the case in some microelectronics, the copper substrate is thin in relation to the volume of solder in the joint an overriding concern is that all of the Cu will be consumed by reaction with Sn to form these intermetallics.This paper reports an investigation into the kinetics of the growth of the interfacial intermetallic, and the consequent reduction in the thickness of the Cu substrate in solder joints made with three alloys, Sn-3.0Ag-0.5Cu, Sn-0.7Cu-0.05Ni and Sn-1.5Bi-0.7Cu-0.05Ni.
Technical Library | 2018-05-17 11:14:52.0
Intermetallic compound (IMC) growth is being studied in earnest in this past decade because of its significant effect the solder joint reliability. It appears that from numerous investigations conducted, excessive growth of IMC could lead to solder joint failure. Leading to this, many attempts has been made to determine the actual IMC thickness. However, precise and true representation of the growth in the actual 3D phenomenon from 2D cross-section investigations has remained unclear. This paper will focus on the measuring the IMC thickness using 3D surface profilometer (Alicona Focus G4). Lead free solder, Sn3.0Ag0.5Cu (SAC305) was soldered onto copper printed circuit board (Cu PCB). The samples were then subjected to thermal cycle (TC) storage process with temperature range from 0 °C to 100 °C for 200 cycles and up to 1000 cycles were completed.
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