Technical Library | 2012-12-17 22:05:22.0
Package on Package (PoP) has become a relatively common component being used in mobile electronics as it allows for saving space in the board layout due to the 3D package layout. To insure device reliability through drop tests and thermal cycling as well as for protecting proprietary programming of the device either one or both interconnect layers are typically underfilled. When underfill is applied to a PoP, or any component for that matter, there is a requirement that the board layout is such that there is room for an underfill reservoir so that the underfill material does not come in contact with surrounding components. The preferred method to dispensing the underfill material is through a jetting process that minimizes the wet out area of the fluid reservoir compared to traditional needle dispensing. To further minimize the wet out area multiple passes are used so that the material required to underfill the component is not dispensed at once requiring a greater wet out area. Dispensing the underfill material in multiple passes is an effective way to reduce the wet out area and decrease the distance that surrounding components can be placed, however, this comes with a process compromise of additional processing time in the underfill dispenser. The purpose of this paper is to provide insight to the inverse relationship that exists between the wet out area of the underfill reservoir and the production time for the underfill process.
Technical Library | 2017-08-28 17:14:41.0
PCB suppliers in the automotive space are vastly accelerating their time to market by using automated optical inspection (AOI) systems during PCB assembly. However, this next-generation technique is not limited in scope to the automotive industry – it has powerful implications for the entire PCB industry.
Technical Library | 2023-10-19 22:03:14.0
Koh Young Technology, the industry leader in True 3D measurement-based inspection solutions, proudly releases another customer success story with Matric Group. This case study shows how Matric Group has leveraged their partnership with Koh Young to be one of the first in the industry to use pre-reflow AOI as a game-changer for line efficiency and improved yield. All while creating a central inspection war room to allow just one person to manage all inline inspection, increasing automation, and control and mitigating talent shortages.
Technical Library | 2011-10-06 13:59:04.0
The desire to have more functionality into increasingly smaller size end products has been pushing the PCB and IC Packaging industry towards High Density Interconnect (HDI) and 3D Packaging (stacked dies, embedded packaged components). Many companies in the high-end consumer electronics market place have been embedding passive chip components on inner PCB and IC Packages for a few years now. However, embedding packaged components on inner layers has remained elusive for the broader market due to lack of proper design tools and high cost of embedding components on inner layers (...) This paper will highlight several key industrialization aspects addressed in the frame of the European funded FP7 HERMES* project to build a manufacturing environment for products with embedded components. The program entered its third year and is now dealing with the manufacturing of functional demonstrators as an introduction to industrialization.
Technical Library | 2015-04-29 03:29:56.0
Statistical Appearance Modelling technology enables an AOI system to “learn real world variation” based on operator interaction with inspection task results. This provides an accurate statistical description of normal variation in a product. With modelling technology, the user does not have to anticipate potential defects as the system will “flag” anything outside the “normal production range”. And, since the system is programmed with real production variation, it is sensitive to small subtle changes enabling reliable defect detection. Autonomous prediction of process variation enables an AOI system to be set up from a single PCB with production-ready performance. Setup time can be
Technical Library | 2013-08-07 21:52:15.0
PCB architectures have continued their steep trend toward greater complexities and higher component densities. For quality control managers and test technicians, the consequence is significant. Their ability to electrically test these products is compounded with each new generation. Probe access to high density boards loaded with micro BGAs using a conventional in-circuit (bed-of-nails) test system is greatly reduced. The challenges and complexity of creating a comprehensive functional test program have all but assured that functional test will not fill the widening gap. This explains why sales of automated-optical and automated X-ray inspection (AOI and AXI) equipment have dramatically risen...
Technical Library | 2019-05-23 21:56:56.0
Automatic on-line shoe sole spraying system: automatic shoe sole spraying system, simple and convenient operation, using 3D vision positioning system. Automatic recognition and automatic generation of spraying trajectory. Robot non-contact spraying gun is used to complete the process of shoe sole spraying with maturity, stability, high speed and high precision along the predetermined trajectory. The automatic generation of spraying trajectory is the realization of shoe sole spraying technology. Shoe sole spraying characteristics: 1.Positioning System: 3D Visual Positioning 2.Components: Intelligent Robot, Laser Scanner, Industrial Computer, Gum Spraying System, Conveyor Belt, Electrical Control System, etc. 3.Spraying time: slightly different according to shoe size and spraying time Fully automatic sole spraying advantages: 1. Simple application: suitable for soles of different specifications, models and sizes 2. Faster speed: 6-8 seconds to complete sole scanning and spraying, superior to similar products at home and abroad. 3. Quality stability: gum spraying trajectory is scheduled, gum dosage is fixed, gum spraying quality is greatly improved. 4. High cost performance: the same performance, the price is only 1/3 of the same type of equipment of European brand. 5. Reduce wear and tear: glue is fully utilized and not wasted, reducing human contact with glue. Intelligent operation advantage manual only need general operation can be automated workshop, mechanical arm automatic spraying glue, accurate spraying, reduce glue waste. Environmental protection effect of long-term close contact with glue seriously affects human health and mechanical work, glue does not directly contact, do not harm the human body. Fully automatic spraying, shoe sole adhesion process for automatic spraying machine, will not cause great challenges! With the deepening of personalized shoemaking, higher requirements have been put forward for the spraying technology in shoemaking process. The method of creating spraying trajectory must be adapted to shoes of different sizes and styles. The automatic generation of spraying trajectory is one of the key technologies to realize the automation of shoe sole spraying process. The method of off-line programming and real-time generation of spraying trajectory for robots based on the three-dimensional CAD model of sole and the data of sole. A new method of generating spray trajectory by scanning the sole of shoe upper with linear structured light sensor is presented. The feasibility of the method is verified by industrial robots. Aiming at the need of generating shoe sole spray rubber trajectory based on line structured light, the format standard of IGES file of three-dimensional model of shoe sole was tested. The shoe sole contour line and the shoe sole surface were extracted, and then the offset curve of the shoe sole contour line on the shoe sole surface was calculated to obtain the spray rubber trajectory. Three-dimensional profilometer is to use structured light to obtain sole information, effectively improve the automatic shoemaking spraying process, which will help to improve the efficiency of shoemaking, improve the quality of footwear products, and promote the development of personalized shoemaking.
Technical Library | 2020-07-08 20:05:59.0
There is a compelling need for functional testing of high-speed input/output signals on circuit boards ranging from 1 gigabit per second (Gbps) to several hundred Gbps. While manufacturing tests such as Automatic Optical Inspection (AOI) and In-Circuit Test (ICT) are useful in identifying catastrophic defects, most high-speed signals require more scrutiny for failure modes that arise due to high-speed conditions, such as jitter. Functional ATE is seldom fast enough to measure high-speed signals and interpret results automatically. Additionally, to measure these adverse effects it is necessary to have the tester connections very close to the unit under test (UUT) as lead wires connecting the instruments can distort the signal. The solution we describe here involves the use of a field programmable gate array (FPGA) to implement the test instrument called a synthetic instrument (SI). SIs can be designed using VHDL or Verilog descriptions and "synthesized" into an FPGA. A variety of general-purpose instruments, such as signal generators, voltmeters, waveform analyzers can thus be synthesized, but the FPGA approach need not be limited to instruments with traditional instrument equivalents. Rather, more complex and peculiar test functions that pertain to high-speed I/O applications, such as bit error rate tests, SerDes tests, even USB 3.0 (running at 5 Gbps) protocol tests can be programmed and synthesized within an FPGA. By using specific-purpose test mechanisms for high-speed I/O the test engineer can reduce test development time. The synthetic instruments as well as the tests themselves can find applications in several UUTs. In some cases, the same test can be reused without any alteration. For example, a USB 3.0 bus is ubiquitous, and a test aimed at fault detection and diagnoses can be used as part of the test of any UUT that uses this bus. Additionally, parts of the test set may be reused for testing another high-speed I/O. It is reasonable to utilize some of the test routines used in a USB 3.0 test, in the development of a USB 3.1 (running at 10 Gbps), even if the latter has substantial differences in protocol. Many of the SI developed for one protocol can be reused as is, while other SIs may need to undergo modifications before reuse. The modifications will likely take less time and effort than starting from scratch. This paper illustrates an example of high-speed I/O testing, generalizes failure modes that are likely to occur in high-speed I/O, and offers a strategy for testing them with SIs within FPGAs. This strategy offers several advantages besides reusability, including tester proximity to the UUT, test modularization, standardization approaching an ATE-agnostic test development process, overcoming physical limitations of general-purpose test instruments, and utilization of specific-purpose test instruments. Additionally, test instrument obsolescence can be overcome by upgrading to ever-faster and larger FPGAs without losing any previously developed design effort. With SIs and tests scalable and upward compatible, the test engineer need not start test development for high-speed I/O from scratch, which will substantially reduce time and effort.
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