Technical Library | 2018-03-28 14:54:36.0
Six decades of legacy experience makes the specification and production of screens and masks to produce repeatable precision results mostly an exercise in matching engineering needs with known ink and substrate performance to specify screen and stencil characteristics. New types of functional and electronic devices, flex circuits and medical sensors, industrial printing, ever finer circuit pitch, downstream additive manufacturing processes coupled with new substrates and inks that are not optimized for the rheological, mechanical and chemical characteristics for the screen printing process are becoming a customer driven norm. Many of these materials do not work within legacy screen making, curing or press set-up parameters. Many new materials and end uses require new screen specifications.This case study presents a DOE based method to pre-test new materials to categorize ink and substrate rheology, compatibility and printed feature requirement to allow more accurate screen recipes and on-press setting expectations before the project enters the production environment where time and materials are most costly and on-press adjustment methods may be constrained by locked, documented or regulatory processes, equipment limitations and employee experience.
Technical Library | 2019-05-06 23:04:05.0
The temperature and humidity test chamber simulate the temperature and humidity, so there are a lot of things customers shoud notice in the process of use, although there is detailed instruction when purchasing the equipment. But some users just know how the device works and start using it. This is very easy to cause problems in the use of the equipment, so Symor intends to describe the safety details during the use of temperature and humidity chamber. 1. Before the test, determine if the sample contains flammable and explosive substances to avoid combustion or explosion during the test. Of course, also make sure there is no flammable and explosive material around the test equipment, otherwise it may cause fire and other accidents. 2, Do not open the chamber door to operate during the experiment, or the gas in the studio may cause the operator to burn and so on. 3. At the end of the test or at the time of regular cleaning of the test chamber, power off the equipment to avoid electrocution accidents. Also, when cutting off the equipment power, pull the power cord to pull out the plug, otherwise it may lead to a rupture of the power cord and so on. You can contact manufacturers if there are some places you donnot understand, do not dismantle and repair the temperature and humidity test chamber without authorization, otherwise it may lead to more serious problems.
Technical Library | 2024-07-24 01:04:35.0
Quad Flat No Leads (QFN) package designs receive more and more attention in electronic industry recently. This package offers a number of benefits including (1) small size, such as a near die size footprint, thin profile, and light weight; (2) easy PCB trace routing due to the use of perimeter I/O pads; (3) reduced lead inductance; and (4) good thermal and electrical performance due to the adoption of exposed copper die-pad technology. These features make the QFN an ideal choice for many new applications where size, weight, electrical, and thermal properties are important. However, adoption of QFN often runs into voiding issue at SMT assembly. Upon reflow, outgassing of solder paste flux at the large thermal pad has difficulty escaping and inevitably results in voiding. It is well known that the presence of voids will affect the mechanical properties of joints and deteriorate the strength, ductility, creep, and fatigue life. In addition, voids could also produce spot overheating, lessening the reliability of the joints.
Technical Library | 2009-05-07 23:23:00.0
Thermal fatigue has been one of the most serious problems for solder joint reliability. Thermo-mechanical fatigue failure is considered to be closely related to micro-structural coarsening (grain/phase growth). Factors that influence the phase growth are studied and measurement methods are discussed, including the preparation of the eutectic solder sample for phase size measurement. Three categories of models used to predict grain growth in polycrystalline materials are presented. Finally, phase growth in solder during high temperature aging and temperature cycling and its use as a damage correlation factor are discussed.
Technical Library | 2015-06-04 19:10:47.0
Integrators and designers of high-reliability systems exert little or no control over component-level plating processes that affect the propensity for tin whiskering. Challenges of how to assure long-term reliability, while continuing to use COTS parts plated with pure tin, continue to arise. An integrated, quantitative, standardized methodology is proposed whereby mitigation levels can be selected that are appropriate for specific applications of pure tin for given end-uses. A system of hardware end-use classification is proposed, together with recommended appropriate risk mitigation approaches. An updated version of the application-specific risk assessment algorithm is presented together with recommended thresholds for acceptability within the context of the hardware classifications.
Technical Library | 2015-06-11 21:20:29.0
The use of bottom terminated components (BTC) has become widespread, specifically the use of Quad Flat No-lead (QFN) packages. The small outline and low height of this package type, improved electrical and thermal performance relative to older packaging technology, and low cost make the QFN/BTC attractive for many applications.Over the past 15 years, the implementation of the QFN/BTC package has garnered a great amount of attention due to the assembly and inspection process challenges associated with the package. The difference in solder application parameters between the center pad and the perimeter pads complicates stencil design, and must be given special attention to balance the dissimilar requirements
Technical Library | 2020-02-19 23:12:55.0
Silver nanowires (Ag NWs) possess excellent optoelectronic properties, which have led to many technology-focused applications of transparent and flexible electronics. Many of these applications require patterning of Ag NWs into desired shapes, for which mask-based and printing-based techniques have been developed and widely used. However, there are still several limitations associated to these techniques. These limitations, such as complicated patterning procedures, limited patterning area, and compromised optical transparency, hamper the efficient fabrication of high-performance Ag NW patterns. Here, we propose a coat-and-print approach for effectively patterning Ag NWs.
Integrated Microwave Packaging Antennas and Circuits Technology (IMPACT) Lab
Technical Library | 2020-10-18 19:35:05.0
Interconnect reliability especially in BGA solder joints and compliant pins are subjected to design parameters which are very critical to ensure product performance at pre-defined shipping condition and user environment. Plating thickness of compliant pin and damping mechanism of electronic system design are key successful factors for this purpose. In additional transportation and material handling process of a computer server system will be affected by shock under certain conditions. Many accessories devices in the server computer system tend to become loose resulting in poor contact or solder intermittent interconnect problems due to the shock load from the transportation and material handling processes.
Technical Library | 2022-08-08 15:06:06.0
Selective soldering has evolved to become a standard production process within the electronics assembly industry, and now accommodates a wide variety of through-hole component formats in numerous applications. Most through-hole components can be easily soldered with the selective soldering process without difficulty however some types of challenging components require additional attention to ensure that optimum quality is maintained. Several high thermal mass components can place demands on the selective soldering process, while the use of specialized solder fixtures, or solder pallets, often places additional thermal demand on the preheating process. Fine-pitch through-hole components and connectors place a different set of demands on the selective soldering process and typically require special attention to lead projection and traverse speed to minimize bridging between adjacent pins. Dual in-line memory module (DIMM) connectors, compact peripheral component interface (cPCI) connectors, coax connectors and other high thermal mass components as well as fine-pitch microconnectors, can present challenges when soldered into backplanes or multilayer printed circuit board assemblies. Adding to this challenge, compact peripheral component interface connectors can present additional solderability issues because of their beryllium copper base metal pins. Key Terms: Selective soldering, drop-jet fluxing, sustained preheating, flux migration, adjacent clearance, lead-to-hole aspect ratio, lead projection, thermal reliefs, gold embrittlement, solderability testing.
Technical Library | 2023-06-12 19:00:21.0
The SMT print process is now very mature and well understood. However as consumers continually push for new electronic products, with increased functionality and smaller form factor, the boundaries of the whole assembly process are continually being challenged. Miniaturisation raises a number of issues for the stencil printing process. How small can we print? What are the tightest pitches? Can we print small deposits next too large for high mix technology assemblies? How closely can we place components for high density products? ...And then on top of this, how can we satisfy some of the cost pressures through the whole supply chain and improve yield in the production process! Today we are operating close to the limits of the stencil printing process. The area ratio rule (the relationship between stencil aperture opening and aperture surface area) fundamentally dictates what can and cannot be achieved in a print process. For next generation components and assembly processes these established rules need to be broken! New stencil printing techniques are becoming available which address some of these challenges. Active squeegees have been shown to push area ratio limits to new boundaries, permitting printing for next generation 0.3CSP technology. Results also indicate there are potential yield benefits for today's leading edge components as well. Stencil coatings are also showing promise. In tests performed to date it is becoming apparent that certain coatings can provide higher yield processing by extending the number of prints that can be performed in-between stencil cleans during a print process. Preliminary test results relating to the stencil coating technology and how they impact miniaturisation and high yield processing will be presented.
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