Technical Library | 2023-01-17 17:58:36.0
Heterogeneous integration has become an important performance enabler as high-performance computing (HPC) demands continue to rise. The focus to enable heterogeneous integration scaling is to push interconnect density limit with increased bandwidth and improved power efficiency. Many different advanced packaging architectures have been deployed to increase I/O wire / area density for higher data bandwidth requirements, and to enable more effective die disaggregation. Embedded Multi-die Interconnect Bridge (EMIB) technology is an advanced, cost-effective approach to in-package high density interconnect of heterogeneous chips, providing high density I/O, and controlled electrical interconnect paths between multiple dice in a package. In emerging architectures, it is required to scale down the EMIB die bump pitch in order to further increase the die-to-die (D2D) communication bandwidth. Aa a result, bump pitch scaling poses significant challenges in the plated solder bump reflow process, e.g., bump height / coplanarity control, solder wicking control, and bump void control. It's crucial to ensure a high-quality solder bump reflow process to meet the final product reliability requirements. In this paper, a combined formic acid based fluxless and vacuum assisted reflow process is developed for fine pitch plated solder bumping application. A high-volume production (HVM) ready tool has been developed for this process.
Technical Library | 2019-06-18 10:18:00.0
ACI Technologies is tasked with decapsulation of electronics components for testing and investigative purposes. In the normal method of decapsulation, an analyst will drill a small indentation, with a rotary tool, in the hermetic sealant material and then apply Nitric acid to eat through the polymeric encapsulant.
Technical Library | 2019-05-24 09:27:33.0
Decapsulation, or de-cap, is a failure analysis technique which involves the removal of material packaging from an integrated circuit (IC). After de-cap, visual inspection by optical microscopy of the internal circuitry may reveal areas where damage is most likely to have occurred. In addition, scanning electron microscopy (SEM) with energy dispersive x-ray spectroscopy (EDS) can identify the composition of any anomalies present after de-cap under higher magnification. The removal process of package material can be done either mechanically or chemically depending on the design of the integrated circuit. With ceramic packaging, de-cap is usually done mechanically by chiseling off the top with a fine razor and small hammer. For plastic packaging, de-cap requires chemical etching by strong acids. In this Tech Tips article, de-cap by chemical etching will be outlined step by step.
Technical Library | 2019-05-29 10:38:59.0
Decapsulation, or de-cap, is a failure analysis technique which involves the removal of material packaging from an integrated circuit (IC). After de-cap, visual inspection by optical microscopy of the internal circuitry may reveal areas where damage is most likely to have occurred. In addition, scanning electron microscopy (SEM) with energy dispersive x-ray spectroscopy (EDS) can identify the composition of any anomalies present after de-cap under higher magnification. The removal process of package material can be done either mechanically or chemically depending on the design of the integrated circuit. With ceramic packaging, de-cap is usually done mechanically by chiseling off the top with a fine razor and small hammer. For plastic packaging, de-cap requires chemical etching by strong acids. In this Tech Tips article, de-cap by chemical etching will be outlined step by step.
Technical Library | 2023-04-17 21:37:32.0
Ionic contamination is a leading cause in the degradation and corrosion of electronic assemblies, leading to lifetime limitation and field failure (Fig. 1). Ionic residue comes from a variety of sources shown in Fig. 2 opposite: Examples of ionic contaminants: * Anions * Cations * Weak Organic Acid
Technical Library | 2015-11-12 19:04:51.0
In order to provide the functionality in today’s electronics, printed circuit boards are approaching the complexity of semiconductors. For flexible circuits with 1 mil lines and spaces, this means no nodules, no pits, and excellent ductility with thinner deposits. One of the areas that has to change to get to this plateau of technology is acid copper plating. Acid copper systems have changed in minor increments since their introduction decades ago. However, the basic cell design using soluble anodes in slabs or baskets has for the most part remained the same. Soluble, phosphorized, copper anodes introduce particulate and limits the ability to control plating distribution.
Technical Library | 2019-12-13 00:39:29.0
Salt spray corrosion chamber can test the ability of material and its protective layer to resist salt mist corrosion, or compare the process quality of similar protective layers, at the same time; this equipment is suitable for parts, electronic components, protective layer of metal material and other industrial products. Salt spray test is divided into neutral and acid test. What is the difference between neutral and acid in salt spray test? First, the temperature applied in the test method is different: Neutral test: a. Laboratory:35°C ±1°C, b. Saturated air drums:47°C ±1°C Acid test: a. Laboratory:50°C ±1°C, b. Saturated air drums:63°C ±1°C Second, the production material is different,neutral test chamber adoptes the traditional PVC plates, acid test chamber asopts PP sheet,which is more high temperature resistance and suits strong acid test. Third. Different test methods satisfied Neutral salt spray chamber according to GB/T 2423.17-2008, GB/T 2423.18-2000, salt spray test method and GB/T 10125-1997, GB/T 10587-2006, GB10593.2-1990, GB/T 1765-1979, GB/T 1771-2007, GB/T 12967.388, GB/T 1705.8-2008, etc. In addition to the test methods specified in the national standard, acid salt spray chamber also needs to expand the standard setting such as IEC,MIL,DIN,ASTM,IS,CNS. Last, Comparison of neutral test solutions China: NaCI distilled water solution NaCI mass concentration (50 ±5) g ≤ l pH value 6.5 ≤ 7.2 United States: distilled water solution NaCI mass concentration 5% ±1% pH value 6.5 ≤ 7.2 Germany: NaCI distilled water solution NaCI mass concentration (50 ±5) g ≤ l pH value 6.5 ≤ 7.2 Japan: NaCI distilled water solution NaCI mass concentration 5% ±1% pH pH value 6.5 ~ 7.2 France: NaCI distilled water solution NaCI mass concentration 5% pH 6.5 ≤ 7.2 https://climatechambers.com/articles&latestnews/difference-between-neutral-and-acid-salt-spray-corrosion-test.html
Technical Library | 2019-07-17 17:56:34.0
The increased demand for electronic devices in recent years has led to an extensive research in the field to meet the requirements of the industry. Electrolytic copper has been an important technology in the fabrication of PCBs and semiconductors. Aqueous sulfuric acid baths are explored for filling or building up with copper structures like blind micro vias (BMV), trenches, through holes (TH), and pillar bumps. As circuit miniaturization continues, developing a process that simultaneously fills vias and plates TH with various sizes and aspect ratios, while minimizing the surface copper thickness is critical. Filling BMV and plating TH at the same time, presents great difficulties for the PCB manufactures. The conventional copper plating processes that provide good via fill and leveling of the deposit tend to worsen the throwing power (TP) of the electroplating bath. TP is defined as the ratio of the deposit copper thickness in the center of the through hole to its thickness at the surface. In this paper an optimization of recently developed innovative, one step acid copper plating technology for filling vias with a minimal surface thickness and plating through holes is presented.
Technical Library | 2019-06-26 23:21:49.0
Copper-filled micro-vias are a key technology in high density interconnect (HDI) designs that have enabled increasing miniaturization and densification of printed circuit boards for the next generation of electronic products. Compared with standard plated through holes (PTHs) copper filled vias provide greater design flexibility, improved signal performance, and can potentially help reduce layer count, thus reducing cost. Considering these advantages, there are strong incentives to optimize the via filling process. This paper presents an innovative DC acid copper via fill formulation, for VCP (Vertical Continues Plating) applications which rapidly fills vias while minimizing surface plating.
Technical Library | 2022-01-05 23:20:33.0
This study aims to present the characterization of five different types of printed circuit boards (PCBs) for use in future recycling processes. PCBs used: motherboards, lead free motherboards, video cards, memory and printer cards. The comminution of the circuit boards was performed using blade mills and hammer mills with 9mm and 6mm meshes, respectively. Throughout the physical processing, analysis was made with stereoscopic optics to ensure that the correct materials had been released. The pre-magnetic separation parts were given a granulometric classification followed by acid digestion and loss on ignition tests.
