Technical Library | 2017-09-14 01:21:52.0
The electronics industry is experiencing a renaissance in semiconductor package technology. A growing number of innovative 3D package assembly methodologies have evolved to enable the electronics industry to maximize their products functionality. By integrating multiple die elements within a single package outline, product boards can be made significantly smaller than their forerunners and the shorter interconnect resulting from this effort has contributed to improving both electrical performance and functional capability. (...) This paper outlines both positive and negative aspects of current 3D package innovations and addresses the challenges facing adopters of silicon and glass based interposer fabrication. The material presented will also reference 3D packaging standards and recognize innovative technologies from a number of industry sources, roadmaps and market forecasts.
Technical Library | 2018-07-18 16:28:26.0
Reduction of first pass defects in the SMT assembly process minimizes cost, assembly time and improves reliability. These three areas, cost, delivery and reliability determine manufacturing yields and are key in maintaining a successful and profitable assembly process. It is commonly accepted that the solder paste printing process causes the highest percentage of yield challenges in the SMT assembly process. As form factor continues to get smaller, the challenge to obtain 100% yield becomes more difficult.This paper will identify defects affecting SMT yields in the printing process and discuss their Root Cause. Outer layer copper weight and surface treatment will also be addressed as to their effect on printability. Experiments using leadless and emerging components will be studied and root cause analysis will be presented
Technical Library | 2019-03-13 15:19:55.0
It is well documented that Nano coatings on SMT stencils offer many benefits to those assembling PWBs. With reduced standard deviation and improved transfer efficiency nano coatings can provide, there is also a cost. As PWB assemblers work to justify the return on investment, one key question continues to arise. What is the durability or life of these coatings and what can be done in the print process to maximize the life of the coatings?This paper addresses durability of the coatings in relation to the number of print cycles and underside wipe cycles applied as well as materials used on the underside wipe process. Different parameters will be applied and data will be collected. The results of this study will be summarized to help those using or considering the use of these nano coatings to improve their print process and suggestions will be given to maximize the life of the coatings.
Technical Library | 2019-05-15 22:26:02.0
As the demand for higher routing density and transfer speed increases, Via-In-Pad Plated Over (VIPPO) has become more common on high-end telecommunications products. The interactions of VIPPO with other features used on a PCB such as the traditional dog-bone pad design could induce solder joints to separate during the second and thereafter reflows. The failure has been successfully reproduced, and the typical failure signature of a joint separation has been summarized.To better understand the solder separation mechanism, this study focuses on designing a test vehicle to address the following three perspectives: PCB material properties, specifically the Z-direction or out-of-plane Coefficient of Thermal Expansion (CTE); PCB thickness and back drill depth; and quantification of the driving force magnitude beyond which the separation is due to occur.
Technical Library | 2011-10-06 13:59:04.0
The desire to have more functionality into increasingly smaller size end products has been pushing the PCB and IC Packaging industry towards High Density Interconnect (HDI) and 3D Packaging (stacked dies, embedded packaged components). Many companies in the high-end consumer electronics market place have been embedding passive chip components on inner PCB and IC Packages for a few years now. However, embedding packaged components on inner layers has remained elusive for the broader market due to lack of proper design tools and high cost of embedding components on inner layers (...) This paper will highlight several key industrialization aspects addressed in the frame of the European funded FP7 HERMES* project to build a manufacturing environment for products with embedded components. The program entered its third year and is now dealing with the manufacturing of functional demonstrators as an introduction to industrialization.
Technical Library | 2019-05-02 13:47:39.0
Automating electronics assembly is complex because many devices are not manufactured on a scale that justifies the cost of setting up robotic systems, which need frequent readjustments as models change. Moreover, robots are only appropriate for a limited part of assembly because small, intricate devices are particularly difficult for them to assemble. Therefore, assembly line designers must minimize operational and readjustment costs by determining the optimal assignment of tasks and resources for workstations. Several research studies address task assignment issues, most of them dealing with robot costs as fixed amount, ignoring operational costs. In real factories, the cost of human resources is constant, whereas robot costs increase with uptime. Thus, human workload must be as large and robot workload as small as possible for the given number of humans and robots. We propose a new task assignment method that establishes a workload balancing that meet precedence and further constraints.
Technical Library | 2024-04-29 21:19:42.0
Over the years, computer vision and machine learning disciplines have considerably advanced the field of automated visual inspection for Printed Circuit Board (PCB-AVI) assurance. However, in practice, the capabilities and limitations of these advancements remain unknown because there are few publicly accessible datasets for PCB visual inspection and even fewer that contain images that simulate realistic application scenarios. To address this need, we propose a publicly available dataset, "FICS-PCB"1, to facilitate the development of robust methods for PCB-AVI. The proposed dataset includes challenging cases from three variable aspects: illumination, image scale, and image sensor. This dataset consists of 9,912 images of 31 PCB samples and contains 77,347 annotated components. This paper reviews the existing datasets and methodologies used for PCBAVI, discusses challenges, describes the proposed dataset, and presents baseline performances using feature engineering and deep learning methods for PCB component classification.
Technical Library | 2019-03-25 12:45:56.0
Work instructions are time consuming to generate for engineers, often requiring regeneration from scratch to address very minor changes. They need to be produced in varying levels of detail, with varying guidelines, for multiple stations, operators and lines. Minor component, station or process changes – down to the modification of an individual BOM component – can cause headaches when attempting to maintain consistency across multiple work instructions that are touched by the change.The solution presented here improves efficiency and saves engineering time by making use of a database driven approach. Manufacturing details, component information, process guidelines, annotations, machine-specific data, and more can be stored in one central database. Any information stored in this single repository can then be modified quickly in one location and automatically propagate seamlessly throughout multiple work instructions. These can be instantly printed out or displayed on screens at appropriately affected stations with the simple click of a button, as opposed to regenerating from scratch, or going in and reviewing many documents to find and update with the change.
Technical Library | 2022-10-11 17:27:08.0
Lead-free flux technology for electronic industry is mainly driven by high soldering temperature, high alloy surface tension, miniaturization, air soldering due to low cost consideration, and environmental concern. Accordingly, the flux features desired included high thermal stability, high resistance against burn-off, high oxidation resistance, high oxygen barrier capability, low surface tension, high fluxing capacity, slow wetting, low moisture pickup, high hot viscosity, and halogen-free. For each of the features listed above, corresponding desired chemical structures can be deduced, and the impact of those structures on flux residue cleanability can be speculated. Overall, lead-free flux technology results in a greater difficulty in cleaning. Cleaner with a better matching solvency for the residue as well as a higher cleaning temperature or agitation are needed. Alkaline and polar cleaner are often needed to deal with the larger quantity of fluxing products. Reactive cleaner is also desired to address the side reaction products such as crosslinked residue.
Technical Library | 2013-01-24 19:16:35.0
The electronics industry has mainly adopted the higher melting point Sn3Ag0.5Cu solder alloys for lead-free reflow soldering applications. For applications where temperature sensitive components and boards are used this has created a need to develop low melting point lead-free alloy solder pastes. Tin-bismuth and tin-bismuth-silver containing alloys were used to address the temperature issue with development done on Sn58Bi, Sn57.6Bi0.4Ag, Sn57Bi1Ag lead-free solder alloy pastes. Investigations included paste printing studies, reflow and wetting analysis on different substrates and board surface finishes and head-in-pillow paste performance in addition to paste-in-hole reflow tests. Voiding was also investigated on tin-bismuth and tin-bismuth-silver versus Sn3Ag0.5Cu soldered QFN/MLF/BTC components. Mechanical bond strength testing was also done comparing Sn58Bi, Sn37Pb and Sn3Ag0.5Cu soldered components. The results of the work are reported.
