Technical Library | 2009-09-09 15:08:19.0
Stencil printing equipment has traditionally been used in the surface mount assembly industry for solder paste printing. In recent years the flexibility of the tool has been exploited for a wide range of materials and processes to aid semiconductor packaging and assembly. One such application has been the deposition of adhesive coatings onto the backside of silicon wafers.
Technical Library | 2017-04-13 10:57:53.0
Parylene has been used for decades as a barrier layer to protect critical devices and components. The parylene deposition process typically requires an adhesion promotion step to make sure the parylene adheres well to the base substrate. Typical adhesion methods don't work well on Kapton and Polyamide, until VSI Parylene came up with a solution.
Technical Library | 2020-09-02 22:14:36.0
The demand for miniaturization and higher density electronic products has continued steadily for years, and this trend is expected to continue, according to various semiconductor technology and applications roadmaps. The printed circuit board (PCB) must support this trend as the central interconnection of the system. There are several options for fine line circuitry. A typical fine line circuit PCB product using copper foil technology, such as the modified semi-additive process (mSAP), uses a thin base copper layer made by pre-etching. The ultrathin copper foil process (SAP with ultrathin copper foil) is facing a technology limit for the miniaturization due to copper roughness and thickness control. The SAP process using sputtered copper is a solution, but the sputtering process is expensive and has issues with via plating. SAP using electroless copper deposition is another solution, but the process involved is challenged to achieve adequate adhesion and insulation between fine-pitch circuitries. A novel catalyst system--liquid metal ink (LMI)--has been developed that avoids these concerns and promotes a very controlled copper thickness over the substrate, targeting next generation high density interconnect (HDI) to wafer-level packaging substrates and enabling 5-micron level feature sizes. This novel catalyst has a unique feature, high density, and atomic-level deposition. Whereas conventional tin-palladium catalyst systems provide sporadic coverage over the substrate surface, the deposited catalyst covers the entire substrate surface. As a result, the catalyst enables improved uniformity of the copper deposition starting from the initial stage while providing higher adhesion and higher insulation resistance compared to the traditional catalysts used in SAP processes. This article discusses this new catalyst process, which both proposes a typical SAP process using the new catalyst and demonstrates the reliability improvements through a comparison between a new SAP PCB process and a conventional SAP PCB process.
Technical Library | 2018-12-26 10:31:05.0
The development of novel interconnection materials for production of electronics is of considerable interest to fulfill increasing demands on interconnect reliability in increasingly demanding environments with respect to temperature extremes, mechanical stresses and/or production limitations. Adhesives are playing an increasingly significant role in the continuously evolving electronics industry. (...)Specific applications will be presented that highlight the feasibility of the technology with respect to conductivity, structural reliability and lifetime standards. The deposition of the novel ICA has been performed using a jet printing technology to ensure both precise and accurate positioning, size and volume delivery.
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