Technical Library | 2021-06-21 19:34:02.0
In this era of electronics miniaturization, high yield and low-cost integrated circuit (IC) substrates play a crucial role by providing a reliable method of high density interconnection of chip to board. In order to maximize substrate real-estate, the distance between Cu traces also known as line and space (L/S) should be minimized. Typical PCB technology consists of L/S larger than 40 µ whereas more advanced wafer level technology currently sits at or around 2 µm L/S. In the past decade, the chip size has decreased significantly along with the L/S on the substrate. The decreasing chip scales and smaller L/S distances has created unique challenges for both printed circuit board (PCB) industry and the semiconductor industry. Fan-out panel-level packaging (FOPLP) is a new manufacturing technology that seeks to bring the PCB world and IC/semiconductor world even closer. While FOPLP is still an emerging technology, the amount of high-volume production in this market space provide a financial incentive to develop innovative solutions in order to enable its ramp up. The most important performance aspect of the fine line plating in this market space is plating uniformity or planarity. Plating uniformity, trace/via top planarity, which measures how flat the top of the traces and vias are a few major features. This is especially important in multilayer processing, as nonuniformity on a lower layer can be transferred to successive layers, disrupting the device design with catastrophic consequences such as short circuits. Additionally, a non-planar surface could also result in signal transmission loss by distortion of the connecting points, like vias and traces. Therefore, plating solutions that provide a uniform, planar profile without any special post treatment are quite desirable.
Technical Library | 2015-03-12 18:26:16.0
Miniaturization and the integration of a growing number of functions in portable electronic devices require an extremely high packaging density for the active and passive components. There are many ways to increase the packaging density and a few examples would be to stack them with Package on Package (PoP), fine pitch CSP's, 01005 and last but not least reduced component to component spacing for active and passive components (...)This paper will discuss different layouts, assembly and material selections to reduce component to component spacing down to 100-125um (4-5mil) from today’s mainstream of 150-200um (6-8mil) component to component spacing.
Technical Library | 2015-04-23 18:48:18.0
Smart phones are complex, costly devices and therefore need to be reworked correctly the first time. In order to meet the ever-growing demand for performance, the complexity of mobile devices has increased immensely, with more than a 70% greater number of packages now found inside of them than just a few years ago. For instance, 1080P HD camera and video capabilities are now available on most high end smart phones or tablet computers, making their production more elaborate and expensive. The printed circuit boards for these devices are no longer considered disposable goods, and their bill of materials start from $150.00, with higher end smart phones going up to $238.00, and tablets well over $300.00.
Technical Library | 2017-06-29 16:39:30.0
Currently there is no industry standard test method for measuring dielectric properties of circuit board materials at frequencies greater than about 10 GHz. Various materials vendors and test labs take different approaches to determine these properties. It is common for these different approaches to yield varying values of key properties like permittivity and loss tangent. The D-24C Task Group of IPC has developed this round robin program to assess these various methods from the "bottom up" to determine if standardized methods can be agreed upon to provide the industry with more accurate and valid characteristics of dielectrics used in high-frequency and high-speed applications.
Technical Library | 2023-05-02 18:50:24.0
Surface-mount PCB components are smaller than their lead-based counterparts and provide a radically higher component density. They are available in a variety of shapes and sizes designated by a series of standardized codes curated by the electronics industry. Of these PCB components, the 0201-sized are the smallest, measuring 0.024 x 0.012 in. (0.6 x 0.3 mm) – that's 70% smaller than the previous 0402 level! The 0201 components are designed to improve reliability in space-constrained applications such as portable electronics like smartphones, tablets, robotics and digital cameras, but require delicate handling during the assembly process. Given the miniaturized dimensions of an 0201 package, it is crucial that the mounting process abide by a series of guidelines regarding the design of the PCB mounting pads and solderable metallization, PCB circuit trace width, solder paste selection, package placement and overages, solder paste reflow, solder stencil screening, and final inspection. It's advisable that one review this information when procuring the services of a PCB assembler.
Technical Library | 2023-05-02 18:54:30.0
Surface-mount PCB components are smaller than their lead-based counterparts and provide a radically higher component density. They are available in a variety of shapes and sizes designated by a series of standardized codes curated by the electronics industry. Of these PCB components, the 0201-sized are the smallest, measuring 0.024 x 0.012 in. (0.6 x 0.3 mm) – that's 70% smaller than the previous 0402 level! The 0201 components are designed to improve reliability in space-constrained applications such as portable electronics like smartphones, tablets, robotics and digital cameras, but require delicate handling during the assembly process.
Technical Library | 2020-09-02 22:02:13.0
With the adoption of Wafer Level Packages (WLP) in the latest generation mobile handsets, the Printed Circuit Board (PCB) industry has also seen the initial steps of High Density Interconnect (HDI) products migrating away from the current subtractive processes towards a more technically adept technique, based on an advanced modified Semi Additive Process (amSAP). This pattern plate process enables line and space features in the region of 20um to be produced, in combination with fully filled, laser formed microvias. However, in order to achieve these process demands, a step change in the performance of the chemical processes used for metallization of the microvia is essential. In the electroless Copper process, the critical activator step often risks cross contamination by the preceding chemistries. Such events can lead to uncontrolled buildup of Palladium rich residues on the panel surface, which can subsequently inhibit etching and lead to short circuits between the final traces. In addition, with more demands being placed on the microvia, the need for a high uniformity Copper layer has become paramount, unfortunately, as microvia shape is often far from ideal, the deposition or "throw" characteristics of the Copper bath itself are also of critical importance. This "high throwing power" is influential elsewhere in the amSAP technique, as it leads to a thinner surface Copper layer, which aids the etching process and enables the ultra-fine features being demanded by today's high end PCB applications. This paper discusses the performance of an electroless Copper plating process that has been developed to satisfy the needs of challenging amSAP applications. Through the use of a radical predip chemistry, the formation, build up and deposition of uncontrolled Pd residues arising from activator contamination has been virtually eradicated. With the adoption of a high throwing power Copper bath, sub 30um features are enabled and microvia coverage is shown to be greatly improved, even in complex via shapes which would otherwise suffer from uneven coverage and risk premature failure in service. Through a mixture of development and production data, this paper aims to highlight the benefits and robust performance of the new electroless Copper process for amSAP applications
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