Technical Library: aes and 01 (Page 1 of 7)

Function and Operational Theory of Condenser Tube Flux Collection System

Technical Library | 2023-01-17 17:50:59.0

Heller's new Condenser Tube Flux Recovery System is designed to provide more efficient flux collection than earlier Heller flux collection systems; while providing minimal down time for inspection and cleaning. The entire system easily fits within the rear of the top shell of an 1800-EXL oven. The system utilizes a different set of top shell caps specially designed to provide the best serviceability of both the flux collection system and maintenance of the heater zone blower motors.

Heller Industries Inc.

Effect of Reflow Profile on SnPb and SnAgCu Solder Joint Shear Force

Technical Library | 2023-01-17 17:27:13.0

Reflow profile has significant impact on solder joint performance because it influences wetting and microstructure of the solder joint. The degree of wetting, the microstructure (in particular the intermetallic layer), and the inherent strength of the solder all factor into the reliability of the solder joint. This paper presents experimental results on the effect of reflow profile on both 63%Sn 37%Pb (SnPb) and 96.5%Sn 3.0%Ag 0.5%Cu (SAC 305) solder joint shear force. Specifically, the effect of the reflow peak temperature and time above solder liquidus temperature are studied. Nine reflow profiles for SAC 305 and nine reflow profiles for SnPb have been developed with three levels of peak temperature (230 o C, 240 o C, and 250 o C for SAC 305; and 195 o C, 205 o C, and 215 o C for SnPb) and three levels of time above solder liquidus temperature (30 sec., 60 sec., and 90 sec.). The shear force data of four different sizes of chip resistors (1206, 0805, 0603, and 0402) are compared across the different profiles. The shear force of the resistors is measured at time 0 (right after assembly). The fracture surfaces have been studied using a scanning electron microscopy (SEM) with energy dispersive spectroscopy (EDS)

Heller Industries Inc.

Using Simulation to Optimize Microvia Placement and Materials to Avoid Failure During Reflow

Technical Library | 2021-12-21 23:11:50.0

This paper cover the following points: - Objective 01: Preprocessing, - Introduction, - Objective 02: Automated FE Scripting, - Objective 03: Postprocessing, Reliability Analysis of PTHs, - Objective 03: Postprocessing, Manufacturability of Microvias

CALCE Center for Advanced Life Cycle Engineering

Investigation of Pad Cratering in Large Flip-Chip BGA using Acoustic Emission

Technical Library | 2013-01-03 20:27:54.0

Electronics assemblies with large flip-chip BGA packages can be prone to either pad cratering or brittle intermetallic (IMC) failures under excessive PCB bending. Pad cratering cracks are not detected by electrical testing or non-destructive inspection methods, yet they pose a long term reliability risk since the cracks may propagate under subsequent loads to cause electrical failure. Since the initiation of pad cratering does not result in an instantaneous electrical signature, detecting the onset of this failure has been challenging. An acoustic emission methodology was recently developed by the authors to detect the onset of pad cratering. The instantaneous release of elastic energy associated with the initiation of an internal crack, i.e., Acoustic Emission (AE), can be monitored to accurately determine the onset of both pad cratering and brittle intermetallic (IMC) failures.

Cisco Systems, Inc.

Stress Analysis and Optimization of a Flip Chip on Flex Electronic Packaging Method for Functional Electronic Textiles

Technical Library | 2020-12-24 02:50:56.0

A method for packaging integrated circuit silicon die in thin flexible circuits has been investigated that enables circuits to be subsequently integrated within textile yarns. This paper presents an investigation into the required materials and component dimensions in order to maximize the reliability of the packaging method. Two die sizes of 3.5 mm×8 mm× 0.53 mm and 2 mm×2 mm×0.1 mm have been simulated and evaluated experimentally under shear load and during bending. The shear and bending experimental results show good agreement with the simulation results and verify the simulated optimal thickness of the adhesive layer. Three underfill adhesives (EP30AO, EP37-3FLF, and Epo-Tek 301 2fl), three highly flexible adhesives (Loctite 4860, Loctite 480, and Loctite 4902), and three substrates (Kapton,Mylar, and PEEK) have been evaluated, and the optimal thickness of each is found. The Kapton substrate, together with the EP37-3FLF adhesive, was identified as the best materials combination with the optimum underfill and substrate thickness identified as 0.05 mm.

University of Southampton

Inline Wire and Cable Identification

Technical Library | 2013-01-30 14:02:44.0

Many OEM’s require that individual wires and cables used in their products be clearly identified with a mark or label. For some, such as in the military and aerospace markets, wire and cable identification (or “wire ID”) is mandatory and the process is governed by stringent specifications, such as SAE AS50881 (formerly MIL5088L). For others, the decision to use wire ID is a voluntary one. This article will describe what type of information is typically identified on wire and cables, concepts for improved productivity, what types of systems are available and the pros and cons of each.

Schleuniger, Inc.

Temperature Cycling and Fatigue in Electronics

Technical Library | 2020-01-01 17:06:52.0

The majority of electronic failures occur due to thermally induced stresses and strains caused by excessive differences in coefficients of thermal expansion (CTE) across materials.CTE mismatches occur in both 1st and 2nd level interconnects in electronics assemblies. 1st level interconnects connect the die to a substrate. This substrate can be underfilled so there are both global and local CTE mismatches to consider. 2nd level interconnects connect the substrate, or package, to the printed circuit board (PCB). This would be considered a "board level" CTE mismatch. Several stress and strain mitigation techniques exist including the use of conformal coating.

DfR Solutions (acquired by ANSYS Inc)

Conformal Coating Why, What, When, and How

Technical Library | 2012-01-05 18:40:07.0

Conformal coating is applied to circuit cards to provide a dielectric layer on an electronic board. This layer functions as a membrane between the board and the environment. With this coating in place, the circuit card can withstand more moisture by incre

DfR Solutions (acquired by ANSYS Inc)

SMT Manufacturability and Reliability in PCB Cavities

Technical Library | 2012-05-31 18:01:31.0

First published in the 2012 IPC APEX EXPO technical conference proceedings. Considering technological advances in multi-depth cavities in the PCB manufacturing industry, various subtopics have materialized regarding the processing and application of such

AT&S

Brass-The Process and Challenges of Laser Cutting

Technical Library | 2024-09-24 19:32:01.0

Reviews the laser technology used to cut brass and hurdles that need tp be overcome.

A-Laser, Inc.

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