Technical Library | 2013-04-12 08:20:15.0
There is much to read about the shifting sands of electronics manufacturing, including current moves by OEMs to alter their EMS relationships to better mitigate risk and cost, while EMS companies look for additional ways in which to adjust their business models in an attempt to improve their profitability. Electronics outsourcing over time evolved from a means to buffer manufacturing demand fluctuations into a wide scale shift in capabilities, in part in order to deal with vastly shorter product life cycles. Following the global economic crash of 2000, aka “the internet bubble,” more and more EMS providers responded by transferring their manufacturing to low cost labour regions, and in particular China.
Technical Library | 2020-09-30 19:23:47.0
There is an increase in the number of optical sensors and cameras being integrated into electronics devices. These go beyond cell phone cameras into automotive sensors, wearables, and other smart devices. The applications can be lens bonding, waveguide imprinting, or other applications where the adhesive is in the optical pathway. To support these various optical applications, new materials with tailorable optical properties are required. There is often a mismatched refractive index between plastic lenses such as PC (Poly Carbonate), COP (Cyclo Olefin Polymer), COC (Cyclo Olefin Copolymer), PMMA (Poly Methyl Methacrylate), and UV curable liquid adhesive. A UV curable liquid adhesive is needed where you can alter the refractive index from 1.470 to 1.730, and maintain high optical performance as yellowness index, haze, and transmittance. This wide range of refractive index possibilities provides optimized optical design. Using particular plastic lens must consider how chemical attack is occurring during the process. Another consideration is that before the UV curable liquid adhesive is cured, chemical raw component can attack the plastic lens which then cracks and delaminates. We will also show engineering and reliability data which defined root cause and provided how optical performance is maintained under different reliability conditions.
Technical Library | 2021-11-17 18:53:50.0
The demand for product miniaturization, especially in the handheld device area, continues to challenge the board assembly industry. The desire to incorporate more functionality while making the product smaller continues to push board design to its limit. It is not uncommon to find boards with castle-like components right next to miniature components. This type of board poses a special challenge to the board assemblers as it requires a wide range of paste volume to satisfy both small and large components. One way to address the printing challenge is to use creative stencil design to meet the solder paste requirement for both large and small components. ... The most important attribute of a stencil is its release characteristic. In other words, how well the paste releases from the aperture. The paste release, in turn, depends on the surface characteristics of the aperture wall and stencil foil. The recent introduction of new technology, nano-coating for both stencil and squeegee blades, has drawn the attention of many researchers. As the name implies, nano-coated stencils and blades are made by a conventional method such as laser-cut or electroformed then coated with nano-functional material to alter the surface characteristics. This study will evaluate nano-coated stencils for passive component printing, including 01005.
Technical Library | 2020-07-08 20:05:59.0
There is a compelling need for functional testing of high-speed input/output signals on circuit boards ranging from 1 gigabit per second (Gbps) to several hundred Gbps. While manufacturing tests such as Automatic Optical Inspection (AOI) and In-Circuit Test (ICT) are useful in identifying catastrophic defects, most high-speed signals require more scrutiny for failure modes that arise due to high-speed conditions, such as jitter. Functional ATE is seldom fast enough to measure high-speed signals and interpret results automatically. Additionally, to measure these adverse effects it is necessary to have the tester connections very close to the unit under test (UUT) as lead wires connecting the instruments can distort the signal. The solution we describe here involves the use of a field programmable gate array (FPGA) to implement the test instrument called a synthetic instrument (SI). SIs can be designed using VHDL or Verilog descriptions and "synthesized" into an FPGA. A variety of general-purpose instruments, such as signal generators, voltmeters, waveform analyzers can thus be synthesized, but the FPGA approach need not be limited to instruments with traditional instrument equivalents. Rather, more complex and peculiar test functions that pertain to high-speed I/O applications, such as bit error rate tests, SerDes tests, even USB 3.0 (running at 5 Gbps) protocol tests can be programmed and synthesized within an FPGA. By using specific-purpose test mechanisms for high-speed I/O the test engineer can reduce test development time. The synthetic instruments as well as the tests themselves can find applications in several UUTs. In some cases, the same test can be reused without any alteration. For example, a USB 3.0 bus is ubiquitous, and a test aimed at fault detection and diagnoses can be used as part of the test of any UUT that uses this bus. Additionally, parts of the test set may be reused for testing another high-speed I/O. It is reasonable to utilize some of the test routines used in a USB 3.0 test, in the development of a USB 3.1 (running at 10 Gbps), even if the latter has substantial differences in protocol. Many of the SI developed for one protocol can be reused as is, while other SIs may need to undergo modifications before reuse. The modifications will likely take less time and effort than starting from scratch. This paper illustrates an example of high-speed I/O testing, generalizes failure modes that are likely to occur in high-speed I/O, and offers a strategy for testing them with SIs within FPGAs. This strategy offers several advantages besides reusability, including tester proximity to the UUT, test modularization, standardization approaching an ATE-agnostic test development process, overcoming physical limitations of general-purpose test instruments, and utilization of specific-purpose test instruments. Additionally, test instrument obsolescence can be overcome by upgrading to ever-faster and larger FPGAs without losing any previously developed design effort. With SIs and tests scalable and upward compatible, the test engineer need not start test development for high-speed I/O from scratch, which will substantially reduce time and effort.
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