Technical Library | 2017-02-09 17:08:44.0
The SMT assembly world, especially within the commercial electronics realm, is dominated by no-clean solder paste technology. A solder paste flux residue that does not require removal is very attractive in a competitive world where every penny of assembly cost counts. One important aspect of the reliability of assembled devices is the nature of the no-clean solder paste flux residue. Most people in this field understand the importance of having a process that renders the solder paste flux residue as benign and inert as possible, thereby ensuring electrical reliability.But, of all the factors that play into the electrical reliability of the solder paste flux residue, is there any impact made by the age of the solder paste and how it was stored? This paper uses J-STD-004B SIR (Surface Insulation Resistance) testing to examine this question.
Technical Library | 2017-08-31 13:43:48.0
Wire bonded packages using conventional copper leadframe have been used in industry for quite some time. The growth of portable and wireless products is driving the miniaturization of packages resulting in the development of many types of thin form factor packages and cost effective assembly processes. Proper optimization of wire bond parameters and machine settings are essential for good yields. Wire bond process can generate a variety of defects such as lifted bond, cracked metallization, poor intermetallic etc. NSOP – non-stick on pad is a defect in wire bonding which can affect front end assembly yields. In this condition, the imprint of the bond is left on the bond pad without the wire being attached. NSOP failures are costly as the entire device is rejected if there is one such failure on any bond pad. The paper presents some of the failure modes observed and the efforts to address NSOP reduction
Technical Library | 2017-11-15 22:49:14.0
While a significant level of voiding can be tolerated in solder joints where electrical conductivity is the main requirement, voiding at any level severely compromises thermal conductivity. For example, in LED lighting modules effective conduction of heat through the 1st level die attach to the substrate and then through the 2nd level attach to the heat sink is critical to performance so that voiding in the solder joints at both levels must be minimized. (...) In this paper, the authors will review the factors that influence the incidence of voids in small and large area solder joints that simulate, respectively, the 1st and 2nd level joints in LED modules and discuss mitigation strategies appropriate to each level. They will also report the results of a study on the effect on the incidence of voids of flux medium formulation and the optimization of the thermal profile to ensure that most of the volatiles are released early in the reflow process.
Technical Library | 2018-11-06 12:42:25.0
Solder paste is a homogeneous, stable suspension of solder powder particles suspended in a flux binder, and is one of the most important process materials today in surface mount technology (SMT). By varying the solder particle size, distribution and shape, as well as the other constituent materials, the rheology and printing performance of solder pastes can be controlled. Paste flow behavior is very important in defining the printing performance of any paste.The purpose of this paper is to study the rheological behavior of SAC (Sn-Ag-Cu) solder paste used for surface mount applications in the electronic industry. The reason why the rheological tests are presented in this paper are two critical sub-processes: aperture filling and paste withdraw. In this paper, we report on the investigation of the rheological profiles, the serrated cone-to-plate system was found as effective in parameter minimizing the wall-slip effect
Technical Library | 2019-07-23 22:33:47.0
The Quad Flat Pack No Leads (QFN) style of leadless packaging [also known as a Land Grid Array (LGA)] is rapidly increasing in us e for wireless, automotive, telecom and many other areas becaus e of its low cost, low stand-off height and excellent thermal and electri cal properties. With the implementation of any new package type, there is always a learning curve for its use in design and processing as well as for the Process and Quality Engineers who have to get to grips with the challenges that these packages bring. Therefore, this paper will provide examples of the common process defects that can be seen with QFNs /LGAs when using optical and x-ray inspection as part of manufacturing quality control. Results of trials conducted on four PCB finishes and using vapour phase and convection reflow will be discussed.
Technical Library | 2020-01-02 12:16:02.0
A customer contacted the Helpline with the concern that parts being used in their assembly may possibly be counterfeit components. The counterfeiting of electronics components is a world-wide problem, and the threat today is even more evident than ever before. Any company, large or small, that manufactures assemblies using electronics components is equally susceptible to using counterfeit devices in their assemblies. In most cases, counterfeit components aren't discovered until after the component has already been placed on a printed circuit board (PCB), usually during first article electrical test. At this point, the only recourse is to debug the circuit to determine the faulty component and rework each PCB already in production to replace the faulty component. As one might easily surmise, this is a rather costly process; world-wide, counterfeit components account for over $15B loss in sales annually!
Technical Library | 2021-05-06 13:48:05.0
In this paper most commonly occurring Bare PCB defects such as Track Cut, Track short and Pad Damages are detected by Image processing techniques. Reference PCB without having any defects is compared with test PCB having defects to identify the defects and x-y coordinates of the center of the defects along with radii are obtained using Difference of Gaussian method and location of the individual type of defects are marked either by similar color or different colors. Result Analysis includes time taken for the inspection of a single defect, multiple similar defects, and multiple different defects. Time taken is ranging from 1.674 to 1.714 seconds if the individual type of defects are marked by different colors and 0.670 to 0.709 seconds if all the identified defects are marked by the same colors.
Technical Library | 2023-11-20 18:18:34.0
When x-ray inspection is used as part of a quality assurance program for any assembled device, steps must be taken early in the design stage to anticipate the use of x-ray inspection later in the development and production processes. This is a lesson that electronic assembly manufacturers learned years ago, and that medical device manufacturers are also discovering. There are several steps involved in learning how to interpret x-ray images, and how to design for x-ray inspection. First, manufacturers need to understand the nature of the x-ray shadow and its modalities; then they need to see how medical device developers and manufacturers are using x-ray inspection; finally, they need to consider taking measures early in the design process to ensure a clear, accurate image when the assembled device undergoes x-ray inspection.
Technical Library | 2023-04-25 22:03:25.0
This report hopes to achieve several goals: 1. Determine the link between bare PWB contamination, soldered assembly contamination and long-term product reliability. 2. Establish measurable limits for bare PWB cleanliness as well as process control limits for both an aqueous as well as a water-soluble soldering process. 3. Determine whether there is any correlation between common, industry-accepted rose/modified rose (omegameter/ionograph type) testing and long term product reliability. 4. Determine the effect PWB plating finish (HASL, Immersion Silver and Cu OSP) has on both bare PWB contamination as well as soldered assembly in a no clean and water soluble process. 5. Determine whether there is a link between percentage of saponifier used to wash soldered assemblies and long-term reliability. 6. Establish a more cost-effective test for manufacturers to use as a process-monitoring tool.
Technical Library | 2013-08-29 19:52:43.0
Au over Ni on Cu is a widely used printed circuit board (PCB) surface finish, under bump metallization (UBM), and component lead metallization. It is generally accepted that less than 3 wt.% Au in Sn-Pb solder joints inhibits formation of detrimental intermetallic compounds (IMC). However, the critical limit for Au content in Pb-free solder joints is not well established. Three surface-mount package platforms, one with a matte Sn surface finish and the others with Ni/Au finish, were soldered to Ni/Au-finished PCB using Sn-3.0Ag 0.5Cu (SAC305) solder, in a realistic manufacturing setting. The assembled boards were divided into three groups: one without any thermal treatment, one subjected to isothermal aging at 125°C for 30 days, and the third group aged at 125°C for 56 days...
