Technical Library | 2022-10-11 20:29:31.0
Electronic assemblies deployed in harsh environments may be subjected to multiple thermal environments during the use-life of the equipment. Often the equipment may not have any macro-indicators of damage such as cracks or delamination. Quantiication of thermal environments during use-life is often not feasible because of the data-capture and storage requirements, and the overhead on core-system functionality. There is need for tools and techniques to quantify damage in deployed systems in absence of macro-indicators of damage without knowledge of prior stress history. The presented PHM framework is targeted towards high reliability applications such as avionic and space systems. In this paper, Sn3.0Ag0.5Cu alloy packages have been subjected to multiple thermal cycling environments including -55 to 125C and 0 to 100C. Assemblies investigated include area-array packages soldered on FR4 printed circuit cards. The methodology involves the use of condition monitoring devices, for gathering data on damage pre-cursors at periodic intervals. Damage-state interrogation technique has been developed based on the Levenberg-Marquardt Algorithm in conjunction with the microstructural damage evolution proxies. The presented technique is applicable to electronic assemblies which have been deployed on one thermal environment, then withdrawn from service and targeted for redeployment in a different thermal environment. Test cases have been presented to demonstrate the viability of the technique for assessment of prior damage, operational readiness and residual life for assemblies exposed to multiple thermo-mechanical environments. Prognosticated prior damage and the residual life show good correlation with experimental data, demonstrating the validity of the presented technique for multiple thermo-mechanical environments.
Technical Library | 2023-07-25 16:50:02.0
Some of the new handheld communication devices offer real challenges to the paste printing process. Normally, there are very small devices like 01005 chip components as well as 0.3 mm pitch uBGA along with other devices that require higher deposits of solder paste. Surface mount connectors or RF shields with coplanarity issues fall into this category. Aperture sizes for the small devices require a stencil thickness in the 50 to 75 um (2-3 mils) range for effective paste transfer whereas the RF shield and SMT connector would like at least 150 um (6 mils) paste height. Spacing is too small to use normal step stencils. This paper will explore a different type of step stencil for this application; a "Two-Print Stencil Process" step stencil. Here is a brief description of a "Two-Print Stencil Process". A 50 to 75 um (2-3 mils) stencil is used to print solder paste for the 01005, 0.3 mm pitch uBGA and other fine pitch components. While this paste is still wet a second in-line stencil printer is used to print all other components using a second thicker stencil. This second stencil has relief pockets on the contact side of the stencil any paste was printed with the first stencil. Design guidelines for minimum keep-out distances between the relief step, the fine pitch apertures, and the RF Shields apertures as well relief pocket height clearance of the paste printed by the first print stencil will be provided.
Technical Library | 2019-11-17 22:46:45.0
Overview of walk-in temperature and humidity chamber: It also belongs to environmental test equipment, it tests whether the product can resist high temperature, low temperature, humidity, or the physical and chemical changes produced under extreme conditions, the walk-in temperature and humidity chamber volume is large, the product is placed, or a large object can be placed, such as automobile, new energy, television and liquid crystal screen, etc. How to do the routine maintenance of the walk-in temperature and humidity chamber: 1. The wet gauze basically, if there is no special case, s/b usually changed once in 3 months 2. The water channel shall be regularly cleaned, including water cup, water tank, etc., so as to prevent the water from being blocked,affect the humidity test. 3. It is forbidden to test the flammable and explosive products inside working room. 4. Clean the chamber on a regular basis 2. How to operate walk-in temperature and humidity chamber: The operation method is same as standard temperature humidity test chamber,the controller is 7-inch LCD programmable color screen, you only need to setthe temperature point---test time--how many cycles need to be tested, This can be done automatically, and the machine will stop automatically when it is complete. If there is any problem during the operation, the corresponding problem point will be displayed on the machine control screen. Walk-in temperature and humidity chamber is a must equipment for reliability test of Automobile,Aerospace,Electronic parts,etc,the operation and maintenance are easy,it is teh tear down mahcine,Climatest engineers will be dispatched to do on-site support,for instance,we will finish commissioning,train customers how to operate,maintain,welcome to follow our company facebook page:https://www.facebook.com/Climatechambers
Technical Library | 2020-11-24 23:01:04.0
The miniaturization trend is driving industry to adopting low standoff components or components in cavity. The cost reduction pressure is pushing telecommunication industry to combine assembly of components and electromagnetic shield in one single reflow process. As a result, the flux outgassing/drying is getting very difficult for devices due to poor venting channel. This resulted in insufficiently dried/burnt-off flux residue. For a properly formulated flux, the remaining flux activity posed no issue in a dried flux residue for no-clean process. However, when venting channel is blocked, not only solvents remain, but also activators could not be burnt off. The presence of solvents allows mobility of active ingredients and the associated corrosion, thus poses a major threat to the reliability. In this work, a new halogen-free no-clean SnAgCu solder paste, 33-76-1, has been developed. This solder paste exhibited SIR value above the IPC spec 100 MΩ without any dendrite formation, even with a wet flux residue on the comb pattern. The wet flux residue was caused by covering the comb pattern with 10 mm × 10 mm glass slide during reflow and SIR testing in order to mimic the poorly vented low standoff components. The paste 33-76-1 also showed very good SMT assembly performance, including voiding of QFN and HIP resistance. The wetting ability of paste 33-76-1 was very good under nitrogen. For air reflow, 33-76-1 still matched paste C which is widely accepted by industry for air reflow process. The above good performance on both non-corrosivity with wet flux residue and robust SMT process can only be accomplished through a breakthrough in flux technology.
Technical Library | 2021-06-21 19:34:02.0
In this era of electronics miniaturization, high yield and low-cost integrated circuit (IC) substrates play a crucial role by providing a reliable method of high density interconnection of chip to board. In order to maximize substrate real-estate, the distance between Cu traces also known as line and space (L/S) should be minimized. Typical PCB technology consists of L/S larger than 40 µ whereas more advanced wafer level technology currently sits at or around 2 µm L/S. In the past decade, the chip size has decreased significantly along with the L/S on the substrate. The decreasing chip scales and smaller L/S distances has created unique challenges for both printed circuit board (PCB) industry and the semiconductor industry. Fan-out panel-level packaging (FOPLP) is a new manufacturing technology that seeks to bring the PCB world and IC/semiconductor world even closer. While FOPLP is still an emerging technology, the amount of high-volume production in this market space provide a financial incentive to develop innovative solutions in order to enable its ramp up. The most important performance aspect of the fine line plating in this market space is plating uniformity or planarity. Plating uniformity, trace/via top planarity, which measures how flat the top of the traces and vias are a few major features. This is especially important in multilayer processing, as nonuniformity on a lower layer can be transferred to successive layers, disrupting the device design with catastrophic consequences such as short circuits. Additionally, a non-planar surface could also result in signal transmission loss by distortion of the connecting points, like vias and traces. Therefore, plating solutions that provide a uniform, planar profile without any special post treatment are quite desirable.
Technical Library | 2020-09-23 21:37:25.0
The need to minimise thermal damage to components and laminates, to reduce warpage-induced defects to BGA packages, and to save energy, is driving the electronics industry towards lower process temperatures. For soldering processes the only way that temperatures can be substantially reduced is by using solders with lower melting points. Because of constraints of toxicity, cost and performance, the number of alloys that can be used for electronics assembly is limited and the best prospects appear to be those based around the eutectic in the Bi-Sn system, which has a melting point of about 139°C. Experience so far indicates that such Bi-Sn alloys do not have the mechanical properties and microstructural stability necessary to deliver the reliability required for the mounting of BGA packages. Options for improving mechanical properties with alloying additions that do not also push the process temperature back over 200°C are limited. An alternative approach that maintains a low process temperature is to form a hybrid joint with a conventional solder ball reflowed with a Bi-Sn alloy paste. During reflow there is mixing of the ball and paste alloys but it has been found that to achieve the best reliability a proportion of the ball alloy has to be retained in the joint, particular in the part of the joint that is subjected to maximum shear stress in service, which is usually the area near the component side. The challenge is then to find a reproducible method for controlling the fraction of the joint thickness that remains as the original solder ball alloy. Empirical evidence indicates that for a particular combination of ball and paste alloys and reflow temperature the extent to which the ball alloy is consumed by mixing with the paste alloy is dependent on the volume of paste deposited on the pad. If this promising method of achieving lower process temperatures is to be implemented in mass production without compromising reliability it would be necessary to have a method of ensuring the optimum proportion of ball alloy left in the joint after reflow can be consistently maintained. In this paper the author explains how the volume of low melting point alloy paste that delivers the optimum proportion of retained ball alloy for a particular reflow temperature can be determined by reference to the phase diagrams of the ball and paste alloys. The example presented is based on the equilibrium phase diagram of the binary Bi-Sn system but the method could be applied to any combination of ball and paste alloys for which at least a partial phase diagram is available or could be easily determined.
Technical Library | 2021-07-20 20:02:29.0
During the manufacturing of printed circuit boards (PCBs) for a Flight Project, it was found that a European manufacturer was building its boards to a European standard that had no requirement for copper wrap on the vias. The amount of copper wrap that was measured on coupons from the panel containing the boards of interest was less than the amount specified in IPC-6012 Rev B, Class 3. To help determine the reliability and usability of the boards, three sets of tests and a simulation were run. The test results, along with results of simulation and destructive physical analysis, are presented in this paper. The first experiment involved subjecting coupons from the panels supplied by the European manufacturer to thermal cycling. After 17 000 cycles, the test was stopped with no failures. A second set of accelerated tests involved comparing the thermal fatigue life of test samples made from FR4 and polyimide with varying amounts of copper wrap. Again, the testing did not reveal any failures. The third test involved using interconnect stress test coupons with through-hole vias and blind vias that were subjected to elevated temperatures to accelerate fatigue failures. While there were failures, as expected, the failures were at barrel cracks. In addition to the experiments, this paper also discusses the results of finite-element analysis using simulation software that was used to model plated-through holes under thermal stress using a steady-state analysis, also showing the main failure mode was barrel cracking. The tests show that although copper wrap was sought as a better alternative to butt joints between barrel plating and copper foil layers, manufacturability remains challenging and attempts to meet the requirements often result in features that reduce the reliability of the boards. Experimental and simulation work discussed in this paper indicate that the standard requirements for copper wrap are not contributing to the overall board reliability, although it should be added that a design with a butt joint is going to be a higher risk than a reduced copper wrap design. The study further shows that procurement requirements for wrap plating thickness from Class 3 to Class 2 would pose little risk to reliability (minimum 5 μm/0.197 mil for all via types).Experimental results corroborated by modeling indicate that the stress maxima are internal to the barrels rather than at the wrap location. In fact, the existence of Cu wrap was determined to have no appreciable effect on reliability.
Technical Library | 2020-05-28 02:19:28.0
Properly functioning printed circuit boards are essential for both manufacturers of electronic devices and also the developers if the overall intent is for the electronic device to function at high capacity. From designing the schematics of the printed circuit boards to testing the products, there is no process of PCB manufacturing and/or assembly that can be taken for granted. While it's true that you can attempt this process on your own, especially if you are in possession of a large scale manufacturing facility, here are a few reasons why it would be a better option to opt for a professional company for PCB manufacturing and assembly. 1. Variety A professional printed circuit boards manufacturing company will be able to offer you a huge variety. You will be able to choose from rigid, flexible, or rigid-flex. What's more, the PCBs will be customized as per the need of the application. 2. Quality Professional and good printed circuit board manufacturing and assembling companies might cost you just a little bit extra but they also guarantee to produce the best results and offer very high quality products. In the end, it is quality that will make the difference between mediocre and a high functioning PCB. 3. Cost Efficiency Since you don't have to waste time or resources on buying equipment to produce the best PCBs or hiring staff to oversee the process, you can actually end up saving money. You can even save on PCB assembly cost by hiring this job out. All you have to do is to negotiate the quote and sit back, relax, and wait for the PCBs to be delivered to you. 4. Eliminate Design Flaws Design engineers hired by PCB manufacturing and assembling companies use the best graphic software to develop and test the schematics of PCBs. This increases the chances of eliminating flaws in the printed circuit boards during the initial design phase. 5. Multilayer PCB Manufacturing and Assembly The process of manufacturing and assembling multilayer PCBs is as intricate as it sounds. All processes of manufacturing and assembling multilayer PCBs require the best machines and trained technicians to pass the quality and functionality tests. Manufacturing and assembling multilayer printed circuit boards yourself is going to cost you a lot. Even the smallest of mistakes during the manufacturing and assembling process might render the entire PCB entirely useless. 6. Save Time PCBs are just a single part of the electronic device. To complete the device, many more pieces would be needed. The manufacturers of the electronic device can hire out the job of manufacturing or assembling the PCBs, which will mean they will have one less chore to do. This, in turn, will save you a lot of time which could be spent on elevating the quality of the product. 7. Experience Experience makes all the difference. It is what makes the name of any company reliable in the market. Long experience of manufacturing and assembling printed circuit boards makes the company well versed in the process and it also makes it an expert to identify design, manufacturing, assembling, and testing needs of certain applications We, at Asia Pacific Circuits, offer these benefits and so much more. For quick turn PCB assembly, PCB manufacturing and PCB designing, you can contact us anytime.
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