Technical Library | 2012-10-25 16:34:02.0
First published in the 2012 IPC APEX EXPO technical conference proceedings. This paper will examine stencil technologies (including Laser and Electroform), Aperture Wall coatings (including Nickel-Teflon coatings and Nano-coatings), and how these parameters influence paste transfer for miniature devices with Area Ratios less than the standard recommended lower limit of .5. A matrix of print tests will be utilized to compare paste transfer and measure the effectiveness of the different stencil configurations. Area Ratios ranging from .32 to .68 will be investigated.
Technical Library | 2017-09-28 16:36:33.0
These nano-coatings also refine the solder paste brick shape giving improved print definition. These two benefits combine to help the solder paste printing process produce an adequate amount of solder paste in the correct position on the circuit board pads. Today, stencil aperture area ratios from 0.66 down to 0.40 are commonly used and make paste printing a challenge. This paper presents data on small area ratio printing for component designs including 01005 Imperial (0402 metric) and smaller 03015 metric and 0201 metric chip components and 0.3 mm and 0.4 mm pitch micro BGAs.
Technical Library | 2018-06-13 11:42:00.0
The art of screen printing solder paste for the surface mount community has been discussed and presented for several decades. However, the impending introduction of passive Metric 0201 devices has reopened the need to re-evaluate the printing process and the influence of stencil architecture. The impact of introducing apertures with architectural dimensions’ sub 150um whilst accommodating the requirements of the standard suite of surface mount connectors, passives and integrated circuits will require a greater knowledge of the solder paste printing process.The dilemma of including the next generation of surface mount devices into this new heterogeneous environment will create area ratio challenges that fall below todays 0.5 threshold. Within this paper the issues of printing challenging area ratio and their associated aspect ratio will be investigated. The findings will be considered against the next generation of surface mount devices.
Technical Library | 2023-05-22 16:42:56.0
Nano-coatings are applied to solder paste stencils with the intent of improving the solder paste printing process. Do they really make a noticeable improvement? The effect of Nano-coatings on solder paste print performance was investigated. Transfer efficiencies were studied across aperture sizes ranging from 0.30 to 0.80 area ratio. Also investigated were the effects of Nano-coatings on transfer efficiencies of tin-lead, lead-free, water soluble, no-clean, and type 3, 4, and 5 solder pastes. Solder paste print performance for each Nano-coating was summarized with respect to all of these variables.
Technical Library | 2023-07-25 16:42:54.0
Printing solder paste for very small components like .3mm pitch CSP's and 01005 Chip Components is a challenge for the printing process when other larger components like RF shields, SMT Connectors, and large chip or resistor components are also present on the PCB. The smaller components require a stencil thickness typically of 3 mils (75u) to keep the Area Ratio greater than .55 for good paste transfer efficiency. The larger components require either more solder paste height or volume, thus a stencil thickness in the range of 4 to 5 mils (100 to 125u). This paper will explore two stencil solutions to solve this dilemma. The first is a "Two Print Stencil" option where the small component apertures are printed with a thin stencil and the larger components with a thicker stencil with relief pockets for the first print. Successful prints with Keep-Outs as small as 15 mils (400u) will be demonstrated. The second solution is a stencil technology that will provide good paste transfer efficiency for Area Ratio's below .5. In this case a thicker stencil can be utilized to print all components. Paste transfer results for several different stencil types including Laser-Cut Fine Grain stainless steel, Laser-Cut stainless steel with and w/o PTFE Teflon coating, AMTX E-FAB with and w/o PTFE coating for Area Ratios ranging from .4 up to .69.
Technical Library | 2013-06-20 14:33:12.0
With today's consumer technologies driving the need for denser and more compact devices, the assembly process for surface mounted devices has becoming increasingly more difficult. With the mixture of components requiring a broader range of print deposition volume, various techniques are in use in an attempt to ensure consistent and appropriate paste volume is achieved. Some of these techniques include step etching a stencil locally on a targeted device, promoting electroformed smooth wall nickel stencils, through to laser cutting newer grade stencil materials. This paper focuses on the relevant attributes that affect the properties of solder paste release and introduces the effects of surface free energy with respect to key elements that make up the stencil printing process.
Technical Library | 2023-06-12 19:00:21.0
The SMT print process is now very mature and well understood. However as consumers continually push for new electronic products, with increased functionality and smaller form factor, the boundaries of the whole assembly process are continually being challenged. Miniaturisation raises a number of issues for the stencil printing process. How small can we print? What are the tightest pitches? Can we print small deposits next too large for high mix technology assemblies? How closely can we place components for high density products? ...And then on top of this, how can we satisfy some of the cost pressures through the whole supply chain and improve yield in the production process! Today we are operating close to the limits of the stencil printing process. The area ratio rule (the relationship between stencil aperture opening and aperture surface area) fundamentally dictates what can and cannot be achieved in a print process. For next generation components and assembly processes these established rules need to be broken! New stencil printing techniques are becoming available which address some of these challenges. Active squeegees have been shown to push area ratio limits to new boundaries, permitting printing for next generation 0.3CSP technology. Results also indicate there are potential yield benefits for today's leading edge components as well. Stencil coatings are also showing promise. In tests performed to date it is becoming apparent that certain coatings can provide higher yield processing by extending the number of prints that can be performed in-between stencil cleans during a print process. Preliminary test results relating to the stencil coating technology and how they impact miniaturisation and high yield processing will be presented.
Technical Library | 2020-10-27 02:02:17.0
Solder powder size is a popular topic in the electronics industry due to the continuing trend of miniaturization of electronics. The question commonly asked is "when should we switch from Type 3 to a smaller solder powder?" Solder powder size is usually chosen based on the printing requirements for the solder paste. It is common practice to use IPC Type 4 or 5 solder powders for stencil designs that include area ratios below the recommended IPC limit of 0.66. The effects of solder powder size on printability of solder paste have been well documented. The size of the solder powder affects the performance of the solder paste in other ways. Shelf life, stencil life, reflow performance, voiding behavior, and reactivity / stability are all affected by solder powder size. Testing was conducted to measure each of these solder paste performance attributes for IPC Type 3, Type 4, Type 5 and Type 6 SAC305 solder powders in both water soluble and no clean solder pastes. The performance data for each size of solder powder in each solder paste flux was quantified and summarized. Guidance for choosing the optimal size of solder powder is given based on the results of this study.
Technical Library | 2020-10-08 00:55:22.0
This article presents the development of a stretchable sensor network with high signal-to-noise ratio and measurement accuracy for real-time distributed sensing and remote monitoring. The described sensor network was designed as an island-and-serpentine type network comprising a grid of sensor "islands" connected by interconnecting "serpentines." A novel high-yield manufacturing process was developed to fabricate networks on recyclable 4-inch wafers at a low cost. The resulting stretched sensor network has 17 distributed and functionalized sensing nodes with low tolerance and high resolution. The sensor network includes Piezoelectric (PZT), Strain Gauge(SG), and Resistive Temperature Detector (RTD) sensors. The design and development of a flexible frame with signal conditioning, data acquisition, and wireless data transmission electronics for the stretchable sensor network are also presented. The primary purpose of the frame subsystem is to convert sensor signals into meaningful data, which are displayed in real-time for an end-user to view and analyze. The challenges and demonstrated successes in developing this new system are demonstrated, including (a) developing separate signal conditioning circuitry and components for all three sensor types (b) enabling simultaneous sampling for PZT sensors for impact detection and (c)configuration of firmware/software for correct system operation. The network was expanded with an in-house developed automated stretch machine to expand it to cover the desired area. The released and stretched network was laminated into an aerospace composite wing with edge-mount electronics for signal conditioning, processing, power, and wireless communication.
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