Technical Library | 2010-05-24 23:47:35.0
Die echte Integration zwischen ATE Flying Prober und Boundary Scan Tester, vorgestellt von Seica, kombiniert das Beste von beiden Testtechniken und multipliziert die Vorteile für den Anwender.
Technical Library | 2021-03-24 01:34:35.0
In this article we propose a generic test script for real=time embedded software system testing, which has been applied to ATE (Automated Test Equipment). After a summary of the theory about embedded software automated test based on test script, the design philosophy and implementation details are described. We have chosen an ATE and integrated python interpreter into it.
Technical Library | 2010-05-20 17:17:03.0
As several industry pundits have expressed in recent years: "the era of 'one test method fits all' seems well behind us." For most test managers with even a modest mix of products, trying to formulate a test policy/philosophy has become a tricky balancing act at the best of times. James Stanbridge, Sales Manager UK for JTAG Technologies, and Steve Lees Managing Director of ATE Solutions look at the options.
Technical Library | 2018-06-20 13:11:57.0
Manufacturers test to ensure that the product is built correctly. Shorts, opens, wrong or incorrectly inserted components, even catastrophically faulty components need to be flagged, found and repaired. When all such faults are removed, however, functional faults may still exist at normal operating speed, or even at lower speeds. Functional board test (FBT) is still required, a process that still relies on test engineers’ understanding of circuit functionality and manually developed test procedures. While functional automatic test equipment (ATE) has been reduced considerably in price, FBT test costs have not been arrested. In fact, FBT is a huge undertaking that can take several weeks or months of test engineering development, unacceptably stretching time to market. The alternative, of selling products that have not undergone comprehensive FBT is equally, if not more, intolerable.
Technical Library | 2020-07-08 20:05:59.0
There is a compelling need for functional testing of high-speed input/output signals on circuit boards ranging from 1 gigabit per second (Gbps) to several hundred Gbps. While manufacturing tests such as Automatic Optical Inspection (AOI) and In-Circuit Test (ICT) are useful in identifying catastrophic defects, most high-speed signals require more scrutiny for failure modes that arise due to high-speed conditions, such as jitter. Functional ATE is seldom fast enough to measure high-speed signals and interpret results automatically. Additionally, to measure these adverse effects it is necessary to have the tester connections very close to the unit under test (UUT) as lead wires connecting the instruments can distort the signal. The solution we describe here involves the use of a field programmable gate array (FPGA) to implement the test instrument called a synthetic instrument (SI). SIs can be designed using VHDL or Verilog descriptions and "synthesized" into an FPGA. A variety of general-purpose instruments, such as signal generators, voltmeters, waveform analyzers can thus be synthesized, but the FPGA approach need not be limited to instruments with traditional instrument equivalents. Rather, more complex and peculiar test functions that pertain to high-speed I/O applications, such as bit error rate tests, SerDes tests, even USB 3.0 (running at 5 Gbps) protocol tests can be programmed and synthesized within an FPGA. By using specific-purpose test mechanisms for high-speed I/O the test engineer can reduce test development time. The synthetic instruments as well as the tests themselves can find applications in several UUTs. In some cases, the same test can be reused without any alteration. For example, a USB 3.0 bus is ubiquitous, and a test aimed at fault detection and diagnoses can be used as part of the test of any UUT that uses this bus. Additionally, parts of the test set may be reused for testing another high-speed I/O. It is reasonable to utilize some of the test routines used in a USB 3.0 test, in the development of a USB 3.1 (running at 10 Gbps), even if the latter has substantial differences in protocol. Many of the SI developed for one protocol can be reused as is, while other SIs may need to undergo modifications before reuse. The modifications will likely take less time and effort than starting from scratch. This paper illustrates an example of high-speed I/O testing, generalizes failure modes that are likely to occur in high-speed I/O, and offers a strategy for testing them with SIs within FPGAs. This strategy offers several advantages besides reusability, including tester proximity to the UUT, test modularization, standardization approaching an ATE-agnostic test development process, overcoming physical limitations of general-purpose test instruments, and utilization of specific-purpose test instruments. Additionally, test instrument obsolescence can be overcome by upgrading to ever-faster and larger FPGAs without losing any previously developed design effort. With SIs and tests scalable and upward compatible, the test engineer need not start test development for high-speed I/O from scratch, which will substantially reduce time and effort.
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