Technical Library: bad tep board (Page 1 of 1)

Solder Paste Measurement: A Yield Improvement Strategy That Helps Improve Profits

Technical Library | 2001-05-03 11:23:09.0

In this age of global competition, world class electronics manufacturers understand that increasing profit margins is accomplished not by increasing price or lowering the quality of components and workmanship, but by increasing production yields. Post-solder inspection ensures that your customers receive good product, but by separating the good boards from the bad boards you only measure yield, not improve it. A yield (and profit) improvement strategy consists of making measurements at critical stages, as early as possible in the assembly process, and adjusting the process parameters to achieve optimal performance.

ASC International

Review of Interconnect Stress Testing Protocols and Their Effectiveness in Screening Microvias

Technical Library | 2016-11-30 15:53:15.0

The use of microvias in Printed Circuit Boards (PCBs) for military hardware is increasing as technology drives us toward smaller pitches and denser circuitry. Along with the changes in technology, the industry has changed and captive manufacturing lines are few and far between. As PCBs get more complicated, the testing we perform to verify the material was manufactured to our requirements before they are used in an assembly needs to be reviewed to ensure that it is sufficient for the technology and meets industry needs to better screen for long-term reliability. The Interconnect Stress Testing (IST) protocol currently used to identify manufacturing issues in plated through holes, blind, or buried vias are not necessarily sufficient to identify problems with microvias. There is a need to review the current IST protocol to determine if it is adequate for finding bad microvias or if there is a more reliable test that will screen out manufacturing inconsistencies. The objective of this research is to analyze a large population of PCB IST coupons to determine if there is a more effective IST test to find less reliable microvias in electrically passing PCB product and to screen for manufacturing deficiencies. The proposed IST test procedure will be supported with visual inspection of corresponding microvia cross sections and Printed Wiring Assembly (PWA) acceptance test results. The proposed screening will be shown to only slightly affect PCB yield while showing a large benefit to screening before PCBs are used in an assembly.

Raytheon

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