Technical Library | 2015-11-05 15:09:27.0
There has been recent activity and interest in Laser-Cut Electroform blank foils as an alternative to normal Electroform stencils. The present study will investigate and compare the print performance in terms of % paste transfer as well the dispersion in paste transfer volume for a variety of Electroform and Laser-Cut stencils with and without post processing treatments. Side wall quality will also be investigated in detail. A Jabil solder paste qualification test board will be used as the PCB test vehicle.
Technical Library | 2022-02-21 19:49:16.0
The ability to undertake non-destructive testing on semiconductor devices, during both their manufacture and their subsequent use in printed circuit boards (PCBs), has become ever more important for checking product quality without compromising productivity. The use of x-ray inspection not only provides a potentially non-destructive test but also allows investigation within optically hidden areas, such as the wire bonding within packages and the quality of post solder reflow of area array devices (e.g. BGAs, CSPs and flip chips).
Technical Library | 2015-02-19 16:54:34.0
Pad cratering is an important failure mode besides crack of solder joint as it’ll pass the regular test but have impact on the long term reliability of the product. A new pin pull test method with solder ball attached and positioning the test board at an angle of 30º is employed to study the strength of pad cratering. This new method clearly reveals the failure mechanism. And a proper way to interpret the finite element analysis (FEA) result is discussed. Impact of pad dimension, width and angle of copper trace on the strength is included. Some findings not included in previous research could help to guide the design for better performance
Technical Library | 2021-07-20 20:02:29.0
During the manufacturing of printed circuit boards (PCBs) for a Flight Project, it was found that a European manufacturer was building its boards to a European standard that had no requirement for copper wrap on the vias. The amount of copper wrap that was measured on coupons from the panel containing the boards of interest was less than the amount specified in IPC-6012 Rev B, Class 3. To help determine the reliability and usability of the boards, three sets of tests and a simulation were run. The test results, along with results of simulation and destructive physical analysis, are presented in this paper. The first experiment involved subjecting coupons from the panels supplied by the European manufacturer to thermal cycling. After 17 000 cycles, the test was stopped with no failures. A second set of accelerated tests involved comparing the thermal fatigue life of test samples made from FR4 and polyimide with varying amounts of copper wrap. Again, the testing did not reveal any failures. The third test involved using interconnect stress test coupons with through-hole vias and blind vias that were subjected to elevated temperatures to accelerate fatigue failures. While there were failures, as expected, the failures were at barrel cracks. In addition to the experiments, this paper also discusses the results of finite-element analysis using simulation software that was used to model plated-through holes under thermal stress using a steady-state analysis, also showing the main failure mode was barrel cracking. The tests show that although copper wrap was sought as a better alternative to butt joints between barrel plating and copper foil layers, manufacturability remains challenging and attempts to meet the requirements often result in features that reduce the reliability of the boards. Experimental and simulation work discussed in this paper indicate that the standard requirements for copper wrap are not contributing to the overall board reliability, although it should be added that a design with a butt joint is going to be a higher risk than a reduced copper wrap design. The study further shows that procurement requirements for wrap plating thickness from Class 3 to Class 2 would pose little risk to reliability (minimum 5 μm/0.197 mil for all via types).Experimental results corroborated by modeling indicate that the stress maxima are internal to the barrels rather than at the wrap location. In fact, the existence of Cu wrap was determined to have no appreciable effect on reliability.
Technical Library | 2021-01-21 02:04:27.0
Traditional single level microvia structures are generally considered the most robust type of interconnection within a printed wire board (PWB) substrate. The rapid implementation of HDI technology now commonly requires between 2, 3 or 4 levels of microvias sequentially processed into the product. Recent OEM funded reliability testing has confirmed that by increasing the levels (stack height) these structures are proving less reliable, when compared to their single or double level counterparts. Recently false positive results have been recorded on products tested with traditional thermal shock testing methodology (cycling between -40°C and 125°C, or 145°C). A number of companies are incurring product failures resulting in increased costs associated with replacing the circuit boards, components and added labour.
Technical Library | 2018-08-22 14:05:42.0
Glass substrates are emerging as a key alternative to silicon and conventional organic substrates for high-density and high-performance systems due to their outstanding dimensional stability, enabling sub-5-µm lithographic design rules, excellent electrical performance, and unique mechanical properties, key in achieving board-level reliability at body sizes larger than 15 × 15 mm2. This paper describes the first demonstration of the board-level reliability of such large, ultrathin glass ball grid array (BGA) packages directly mounted onto a system board, considering both their thermal cycling and drop-test performances.
Technical Library | 2021-08-23 01:53:13.0
After the equipment was introduced, the production capacity was increased by 20%, and the number of operators was reduced by 50%. Employees' salary expenses have been reduced by RMB 120,000 per year, and the pass-through rate has increased by 10% .
Technical Library | 2014-02-06 17:49:48.0
Many electronics manufacturers perform SIR testing to evaluate solder materials and sometimes the results they obtain differ significantly from those stated by the solder material provider. The difference in the results is typically the result of SIR coupon preparation. This paper will discuss the issue of SIR coupon preparation, board cleaning techniques, and how board cleanliness directly affects SIR results.
Technical Library | 2022-10-31 17:30:40.0
This paper presents a quantitative analysis of solder joint reliability data for lead-free Sn-Ag-Cu (SAC) and mixed assembly (SnPb + SAC) circuit boards based on an extensive, but non-exhaustive, collection of thermal cycling test results. The assembled database covers life test results under multiple test conditions and for a variety of components: conventional SMT (LCCCs, resistors), Ball Grid Arrays, Chip Scale Packages (CSPs), wafer-level CSPs, and flip-chip assemblies with and without underfill. First-order life correlations are developed for SAC assemblies under thermal cycling conditions. The results of this analysis are put in perspective with the correlation of life test results for SnPb control assemblies. Fatigue life correlations show different slopes for SAC versus SnPb assemblies, suggesting opposite reliability trends under low or high stress conditions. The paper also presents an analysis of the effect of Pb contamination and board finish on lead-free solder joint reliability. Last, test data are presented to compare the life of mixed solder assemblies to that of standard SnPb assemblies for a wide variety of area-array components. The trend analysis compares the life of area-array assemblies with: 1) SAC balls and SAC or SnPb paste; 2) SnPb balls assembled with SAC or SnPb paste.
Technical Library | 2012-05-03 20:40:10.0
First published in the 2012 IPC APEX EXPO technical conference proceedings. Increased pressures to reduce time to market and time to volume have forced many manufacturers of populated printed circuit boards to rely on capacitively coupled, un-powered, vec
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