Technical Library | 2013-01-17 15:37:21.0
A problem exists with electroless nickel / immersion gold (ENIG) surface finish on some pads, on some boards, that causes the solder joint to separate from the nickel surface, causing an open. The solder has wet and dissolved the gold. A weak tin to nickel intermetallic bond initially occurs, but the intermetallic bond cracks and separates when put under stress. Since the electroless nickel / immersion gold finish performs satisfactory in most applications, there had to be some area within the current chemistry process window that was satisfactory. The problem has been described as a 'BGA Black Pad Problem' or by HP as an 'Interfacial Fracture of BGA Packages…'[1]. A 24 variable experiment using three different chemistries was conducted during the ITRI (Interconnect Technology Research Institute) ENIG Project, Round 1, to investigate what process parameters of the chemical matrix were potentially satisfactory to use and which process parameters of the chemical matrix need to be avoided. The ITRI ENIG Project has completed Round 1 of testing and is now in the process of Round 2 TV (Test Vehicle) build.
Technical Library | 2013-12-27 10:39:21.0
The head-in-pillow defect has become a relatively common failure mode in the industry since the implementation of Pb-free technologies, generating much concern. A head-in-pillow defect is the incomplete wetting of the entire solder joint of a Ball-Grid Array (BGA), Chip-Scale Package (CSP), or even a Package-On-Package (PoP) and is characterized as a process anomaly, where the solder paste and BGA ball both reflow but do not coalesce. When looking at a cross-section, it actually looks like a head has pressed into a soft pillow. There are two main sources of head-in-pillow defects: poor wetting and PWB or package warpage. Poor wetting can result from a variety of sources, such as solder ball oxidation, an inappropriate thermal reflow profile or poor fluxing action. This paper addresses the three sources or contributing issues (supply, process & material) of the head-in-pillow defects. It will thoroughly review these three issues and how they relate to result in head-in pillow defects. In addition, a head-in-pillow elimination plan will be presented with real life examples will be to illustrate these head-in-pillow solutions.
Technical Library | 2015-08-20 15:18:38.0
Increasing system integration and component densities continue to significantly reduce the opportunity to access nets using standard test points. Over time the size of test points has been drastically reduced (as small as 0.5 mm in diameter) but current product design parameters have created space and access limitations that remove even the option for these test points. Many high speed signal lines have now been restricted to inner layers only. Where surface traces are still available for access, bead probe technology is an option that reduces test point space requirements as well as their effects on high speed nets and distributes mechanical loading away from BGA footprints enabling test access and reducing the risk of mechanical defects associated with the concentration of ICT spring forces under BGA devices. Building on Celestica's previous work characterizing contact resistance associated with Pr-free compatible surface finishes and process chemistry; this paper will describe experimentation to define a robust process window for the implementation of bead probe and similar bump technology that is compatible with standard Pb-free assembly processes. Test Vehicle assembly process, test methods and "Design of Experiments" will be described. Bead Probe formation and deformation under use will also be presented along with selected results.
Technical Library | 2013-01-03 20:27:54.0
Electronics assemblies with large flip-chip BGA packages can be prone to either pad cratering or brittle intermetallic (IMC) failures under excessive PCB bending. Pad cratering cracks are not detected by electrical testing or non-destructive inspection methods, yet they pose a long term reliability risk since the cracks may propagate under subsequent loads to cause electrical failure. Since the initiation of pad cratering does not result in an instantaneous electrical signature, detecting the onset of this failure has been challenging. An acoustic emission methodology was recently developed by the authors to detect the onset of pad cratering. The instantaneous release of elastic energy associated with the initiation of an internal crack, i.e., Acoustic Emission (AE), can be monitored to accurately determine the onset of both pad cratering and brittle intermetallic (IMC) failures.
Technical Library | 2007-11-29 17:20:31.0
Programs have been developed to predict the expected yield of flip chip assemblies, based on substrate design and the statistics of actual manufactured boards, as well as placement machine accuracy, variations in bump sizes, and possible substrate warpage. These predictions and the trends they reveal can be used to direct changes in design so that defect levels will fall below the acceptable limits. Shapes of joints are calculated analytically, or when this is not possible, numerically by means of a public domain program called Surface Evolver. The method is illustrated with an example involving the substrate for a flip chip BGA.
Technical Library | 2013-03-12 13:25:18.0
High density and miniaturized circuit assemblies challenge the solder paste printing process. The use of small components such as 0201, 01005 and μBGA devices require good paste release to prevent solder paste bridging and misalignment. When placing these miniaturized components, taller paste deposits are often required. To improve solder paste deposition, a nano-coating is applied to laser cut stencils to improve transfer efficiency. One concern is the compatibility of the nano-coating with cleaning agents used in understencil wipe and stencil cleaning. The purpose of this research is to test the chemical compatibility of common cleaning agents used in understencil wipe and stencil cleaning processes.Compatibility of Cleaning Agents With Nano-Coated Stencils
Technical Library | 2013-06-13 15:31:24.0
Electromigration (EM) is a mass transportation mechanism driven by electron wind force, thermal gradient, chemical potential and stress gradient. According to Moore’s law, number of transistors on integrated circuits (ICs) doubles approximately every 2 years. Moore’s law holds true since its introduction in 1970s. This insatiable demand for smaller ICs size, larger integration and higher Input/Output (IO) count of microelectronics has made ball grid array (BGA) the most promising connection type in electronic packaging industry. This trend, however, renders EM reliability of solders joints a major bottleneck to hinder further development of electronics industry...
Electronic Packaging Laboratory, State University of New York
Technical Library | 2014-01-23 16:49:55.0
As reliability requirements increase, especially for defense and aerospace applications, the need to characterize components used in electronic assembly also increases. OEM and EMS companies look to perform characterizations as early as possible in the process to be able to limit quality related issues and improve both assembly yields and ultimate device reliability. In terms of BGA devices, higher stress conditions, RoHS compatible materials and increased package densities tend to cause premature failures in intermetallic layers. Therefore it is necessary to have a quantitative and qualitative test methodology to address these interfaces.
Technical Library | 2014-04-11 16:03:15.0
In order to meet the increasing demand of device miniaturization, high speed, more memory, more function, low cost, and more flexibility in device design and manufacturing chain, underfilling has increasingly become an essential process for the good reliability of electronic devices. Filled capillary underfill has been selected for use in package-level where there is large thermal stress caused by CTE mismatch issue, but the underfill is usually not reworkable. Unfilled capillary underfill has been used for board-level application such as BGA/CSP, POP, WL-CSP where there is need for mechanical shock resistance, the underfill is usually reworkable.
Technical Library | 2014-05-08 16:34:16.0
Bare die mounting on multi-device substrates has been in use in the microelectronics industry since the 1960s. The aerospace industry’s hybrid modules and IBM’s Solid Logic Technology were early implementations that were developed in the 1960’s. The technologies progressed on a steady level until the mid 1990’s when, with the advent of BGA packaging and chip scale packages, the microelectronics industry started a wholesale move to area array packaging. This paper outlines the challenges for both traditional wire-bond die attached to a printed wiring board (pwb), to the more recent applications of bumped die attached to a high performance substrate.
A US manufacturer of quality hand tools for those engaged in the repair, rework, R & D, testing, and assembly of electronic components and printed circuit boards from Through Hole to 2Mil Pitch Surface Mount.
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Portland, ME USA
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