Technical Library | 2018-08-22 14:05:42.0
Glass substrates are emerging as a key alternative to silicon and conventional organic substrates for high-density and high-performance systems due to their outstanding dimensional stability, enabling sub-5-µm lithographic design rules, excellent electrical performance, and unique mechanical properties, key in achieving board-level reliability at body sizes larger than 15 × 15 mm2. This paper describes the first demonstration of the board-level reliability of such large, ultrathin glass ball grid array (BGA) packages directly mounted onto a system board, considering both their thermal cycling and drop-test performances.
Technical Library | 2013-06-13 15:31:24.0
Electromigration (EM) is a mass transportation mechanism driven by electron wind force, thermal gradient, chemical potential and stress gradient. According to Moore’s law, number of transistors on integrated circuits (ICs) doubles approximately every 2 years. Moore’s law holds true since its introduction in 1970s. This insatiable demand for smaller ICs size, larger integration and higher Input/Output (IO) count of microelectronics has made ball grid array (BGA) the most promising connection type in electronic packaging industry. This trend, however, renders EM reliability of solders joints a major bottleneck to hinder further development of electronics industry...
Electronic Packaging Laboratory, State University of New York
Technical Library | 2021-09-08 14:10:12.0
The Pb-Free Alloy Characterization Program sponsored by International Electronics Manufacturing Initiative (iNEMI) is conducting an extensive investigation using accelerated temperature cycling (ATC) to evaluate ball grid array (BGA) thermal fatigue performance of 12 commercial or developmental Sn based Pb-free solder alloys. This paper presents the initial findings from a specific subset of the temperature cycling test matrix. The focus is on comparing alloy performance for two of the most commonly specified temperature cycles, 0 to 100 °C and -40 to 125 °C.
Technical Library | 2013-03-14 17:19:28.0
Commercial-off-the-shelf ball/column grid array packaging (COTS BGA/CGA) technologies in high reliability versions are now being considered for use in a number of National Aeronautics and Space Administration (NASA) electronic systems. Understanding the process and quality assurance (QA) indicators for reliability are important for low-risk insertion of these advanced electronic packages. This talk briefly discusses an overview of packaging trends for area array packages from wire bond to flip-chip ball grid array (FCBGA) as well as column grid array (CGA). It then presents test data including manufacturing and assembly board-level reliability for FCBGA packages with 1704 I/Os and 1-mm pitch, fine pitch BGA (FPBGA) with 432 I/Os and 0.4-mm pitch, and PBGA with 676 I/Os and 1.0-mm pitch packages. First published in the 2012 IPC APEX EXPO technical conference proceedings.
Technical Library | 2017-06-22 17:11:53.0
C-mode scanning acoustic microscopy (C-SAM) is a non-destructive inspection technique showing the internal features of a specimen by ultrasound. The C-SAM is the preferred method for finding “air gaps” such as delamination, cracks, voids, and porosity. This paper presents evaluations performed on various advanced packages/assemblies especially flip-chip die version of ball grid array/column grid array (BGA/CGA) using C-SAM equipment. For comparison, representative x-ray images of the assemblies were also gathered to show key defect detection features of the two non-destructive techniques.
Technical Library | 2014-03-06 19:04:07.0
Over the last few years, there has been an increase in the rate of Head-in-Pillow component soldering defects which interrupts the merger of the BGA/CSP component solder spheres with the molten solder paste during reflow. The issue has occurred across a broad segment of industries including consumer, telecom and military. There are many reasons for this issue such as warpage issues of the component or board, ball co-planarity issues for BGA/CSP components and non-wetting of the component based on contamination or excessive oxidation of the component coating. The issue has been found to occur not only on lead-free soldered assemblies where the increased soldering temperatures may give rise to increase component/board warpage but also on tin-lead soldered assemblies.
Technical Library | 2013-08-14 14:06:48.0
This paper discusses how to successfully profile a printed circuit board when reworking Ball Grid Array and Chip Scale Packages.
Technical Library | 2015-02-12 16:57:56.0
Electronic systems are known to be affected by the environmental and mechanical conditions, such as humidity, temperature, thermal shocks and vibration. These adverse environmental operating conditions, with time, could degrade the mechanical efficiency of the system and might lead to catastrophic failures.The aim of this study is to investigate the mechanical integrity of lead-free ball grid array (BGA) solder joints subjected to isothermal ageing at 150°C for up to 1000 hours. Upon ageing at 150°C the Sn-3.5Ag solder alloy initially age-softened for up to 200 hours. This behaviour was linked to the coarsening of grains. When aged beyond 200 hours the shear strength was found to increase up to 400 hours. This age-hardening was correlated with precipitation of hard Ag3Sn particles in Sn matrix. Further ageing resulted in gradual decrease in shear strength. This can be explained as the combined effect of precipitation coarsening and growth of intermetallic layer. The fractured surfaces of the broken solder balls were also investigated under a Scanning Electron Microscope. The shear failures were generally due to ductile fractures in bulk solders irrespective of the ageing time.
Technical Library | 2017-07-06 15:50:17.0
Head-in-pillow (HiP) is a BGA defect which happens when solder balls and paste can't contact well during reflow soldering. Package warpage was one of the major reasons for HiP formation. In this paper, package warpage was measured and simulated. It was found that the package warpage was sensitive to the thickness of inside chips. A FEM method considering viscoelastic property of mold compound was introduced to simulate package warpage. The CTE mismatch was found contributes to more than 90% of the package warpage value when reflowing at the peak temperature. A method was introduced to measure the warpage threshold, which is the smallest warpage value that may lead to HiP. The results in different atmospheres showed that the warpage threshold was 50μm larger in N2 than that in air, suggesting that under N2 atmosphere the process window for HiP defects was larger than that under air, which agreed with the experiments.
Technical Library | 2020-09-23 21:37:25.0
The need to minimise thermal damage to components and laminates, to reduce warpage-induced defects to BGA packages, and to save energy, is driving the electronics industry towards lower process temperatures. For soldering processes the only way that temperatures can be substantially reduced is by using solders with lower melting points. Because of constraints of toxicity, cost and performance, the number of alloys that can be used for electronics assembly is limited and the best prospects appear to be those based around the eutectic in the Bi-Sn system, which has a melting point of about 139°C. Experience so far indicates that such Bi-Sn alloys do not have the mechanical properties and microstructural stability necessary to deliver the reliability required for the mounting of BGA packages. Options for improving mechanical properties with alloying additions that do not also push the process temperature back over 200°C are limited. An alternative approach that maintains a low process temperature is to form a hybrid joint with a conventional solder ball reflowed with a Bi-Sn alloy paste. During reflow there is mixing of the ball and paste alloys but it has been found that to achieve the best reliability a proportion of the ball alloy has to be retained in the joint, particular in the part of the joint that is subjected to maximum shear stress in service, which is usually the area near the component side. The challenge is then to find a reproducible method for controlling the fraction of the joint thickness that remains as the original solder ball alloy. Empirical evidence indicates that for a particular combination of ball and paste alloys and reflow temperature the extent to which the ball alloy is consumed by mixing with the paste alloy is dependent on the volume of paste deposited on the pad. If this promising method of achieving lower process temperatures is to be implemented in mass production without compromising reliability it would be necessary to have a method of ensuring the optimum proportion of ball alloy left in the joint after reflow can be consistently maintained. In this paper the author explains how the volume of low melting point alloy paste that delivers the optimum proportion of retained ball alloy for a particular reflow temperature can be determined by reference to the phase diagrams of the ball and paste alloys. The example presented is based on the equilibrium phase diagram of the binary Bi-Sn system but the method could be applied to any combination of ball and paste alloys for which at least a partial phase diagram is available or could be easily determined.
.png)
