Technical Library | 2007-01-31 15:17:04.0
The goal of this project is to evaluate the reliability of lead-free BGA solder joints with a variety of different pad sizes using several different BGA rework methods. These methods included BGAs reworked with both flux only and solder paste attachment techniques and with or without the use of the BEST stay in place StencilQuick™. The daisy chained test boards were placed into a thermal test chamber and cycled between -25ºC to 125ºC over a 30 minute cycle with a 30 minute dwell on each end of the cycle. Each BGA on the board was wired and the continuity assessed during the 1000 cycles the test samples were in the chamber.
Technical Library | 2007-02-01 10:08:40.0
The increased replacement of high lead count SMT devices with BGAs and other high ball count area array packages has brought increased challenges to PCB rework and repair. Often solder mask areas surrounding BGA pad areas are damaged when components are removed.
Technical Library | 2007-08-16 13:34:31.0
While experienced inspectors may be able to determine the aesthetic differences between a lead-free PCB assembly and a tin-lead version, one cannot rely on the "experienced eye". "Less wetting out to the pad edges" (Figure A) and "graininess and lack of shininess of the solder joint" (Figure B) are typical comments about some lead-free solder joints. However, in cases where a Nitrogen atmosphere was present during the reflow of the solder joint (Figure C), there will be little visual differences between the lead free alloys and their tin-lead counterparts.
Technical Library | 2009-12-03 14:27:29.0
This paper provides additional data in support of shelf life extension for BGA and Die Size BGA (DSBGA) Packages.
Technical Library | 2008-04-08 17:42:27.0
Concern about the failure of lead-free BGA packages when portable devices such as cell phones are accidentally dropped and a general concern about the resistance of these packages under shock loading has prompted an interest in the impact strength of the soldered BGA connection. This paper reports the results of the measurement of the impact strength of lead-free 0.5±0.01mm diameter BGA spheres on 0.42mm solder mask defined pads on copper/OSP and ENIG substrates using recently developed equipment that can load individual BGA spheres at high strain rates in shear and tension.
Technical Library | 2013-01-03 20:27:54.0
Electronics assemblies with large flip-chip BGA packages can be prone to either pad cratering or brittle intermetallic (IMC) failures under excessive PCB bending. Pad cratering cracks are not detected by electrical testing or non-destructive inspection methods, yet they pose a long term reliability risk since the cracks may propagate under subsequent loads to cause electrical failure. Since the initiation of pad cratering does not result in an instantaneous electrical signature, detecting the onset of this failure has been challenging. An acoustic emission methodology was recently developed by the authors to detect the onset of pad cratering. The instantaneous release of elastic energy associated with the initiation of an internal crack, i.e., Acoustic Emission (AE), can be monitored to accurately determine the onset of both pad cratering and brittle intermetallic (IMC) failures.
Technical Library | 2021-12-16 01:45:05.0
In the 1990's, both BGA (Ball Grid Array) and CSP (Chip Size Package) are entering their end in the front-end packaging materials and process technology. Both BGA and CSP like SMD (Surface Mount Device) from the I 980's and THD (Through-Hole mount Device) from the 1970's are reaching its own impasse in terms of maximizing its electrical, mechanical, and thermal performances, size, weight, and reliability.
Technical Library | 2023-07-25 16:25:56.0
This paper address two significant applications of stencils in advance packaging field: 1. Ultra-Thin stencils for miniature component (0201m) assembly; 2. Deep Cavity stencils for embedded (open cavity) packaging. As the world of electronics continues to evolve with focus on smaller, lighter, faster, and feature-enhanced high- performing electronic products, so are the requirement for complex stencils to assemble such components. These stencil thicknesses start from less than 25um with apertures as small as 60um (or less). Step stencils are used when varying stencil thicknesses are required to print into cavities or on elevated surfaces or to provide relief for certain features on a board. In the early days of SMT assembly, step stencils were used to reduce the stencil thickness for 25 mil pitch leaded device apertures. Thick metal stencils that have both relief-etch pockets and reservoir step pockets are very useful for paste reservoir printing. Electroform Step-Up Stencils for ceramic BGA's and RF Shields are a good solution to achieve additional solder paste height on the pads of these components as well as providing exceptional paste transfer for smaller components like uBGAs and 0201s. As the components are getting smaller, for example 0201m, or as the available real estate for component placement on a board is getting smaller – finer is the aperture size and the pitch on the stencils. Aggressive distances from step wall to aperture are also required. Ultra-thin stencils with thicknesses in the order of 15um-40um with steps of 15um are used to obtain desired print volumes. Stencils with thickness to this order can be potential tools even to print for RDLs in the package.
Technical Library | 2024-07-24 01:18:03.0
Quad Flat No-Lead (QFN) packages has become very popular in the industry and are widely used in many products. These packages have different size and pin counts, but they have a common feature: thermal pad at the bottom of device. The thermal pad of the leadless QFN provides efficient heat dissipation from the component to PCB. In many cases, arrays of the thermal via under the component is used to dissipate heat from the device. However, thermal vias can create more voids or result in solder protrusion onto the secondary side.
Technical Library | 2024-07-24 01:04:35.0
Quad Flat No Leads (QFN) package designs receive more and more attention in electronic industry recently. This package offers a number of benefits including (1) small size, such as a near die size footprint, thin profile, and light weight; (2) easy PCB trace routing due to the use of perimeter I/O pads; (3) reduced lead inductance; and (4) good thermal and electrical performance due to the adoption of exposed copper die-pad technology. These features make the QFN an ideal choice for many new applications where size, weight, electrical, and thermal properties are important. However, adoption of QFN often runs into voiding issue at SMT assembly. Upon reflow, outgassing of solder paste flux at the large thermal pad has difficulty escaping and inevitably results in voiding. It is well known that the presence of voids will affect the mechanical properties of joints and deteriorate the strength, ductility, creep, and fatigue life. In addition, voids could also produce spot overheating, lessening the reliability of the joints.
