Technical Library | 2013-01-17 15:34:33.0
The use of an electroless nickel, immersion gold (ENIG) surface finish comes with the inherent potential risk of Black Pad failures that can cause fracture embrittlement at the interface between the solder and the metal pad. As yet, there is no conclusive agreed solution to effectively eliminate Black Pad failures. The case studies presented are intended to add to the understanding of the Black Pad failure mechanism and to identify both the plating and the subsequent assembly processes and conditions that can help to prevent the likelihood of Black Pad occurring.
Technical Library | 2013-12-27 10:39:21.0
The head-in-pillow defect has become a relatively common failure mode in the industry since the implementation of Pb-free technologies, generating much concern. A head-in-pillow defect is the incomplete wetting of the entire solder joint of a Ball-Grid Array (BGA), Chip-Scale Package (CSP), or even a Package-On-Package (PoP) and is characterized as a process anomaly, where the solder paste and BGA ball both reflow but do not coalesce. When looking at a cross-section, it actually looks like a head has pressed into a soft pillow. There are two main sources of head-in-pillow defects: poor wetting and PWB or package warpage. Poor wetting can result from a variety of sources, such as solder ball oxidation, an inappropriate thermal reflow profile or poor fluxing action. This paper addresses the three sources or contributing issues (supply, process & material) of the head-in-pillow defects. It will thoroughly review these three issues and how they relate to result in head-in pillow defects. In addition, a head-in-pillow elimination plan will be presented with real life examples will be to illustrate these head-in-pillow solutions.
Technical Library | 2016-01-21 16:52:27.0
Solder paste has long been viewed as "black magic". This "black magic" can easily be dispelled through a solder paste evaluation. Unfortunately, solder paste evaluation can be a challenge for electronic assemblers. Interrupting the production schedule to perform an evaluation is usually the first hurdle. Choosing the solder paste properties to test is simple, but testing for these properties can be difficult. Special equipment or materials may be required depending upon the tests that are chosen. Once the testing is complete, how does one make the decision to choose a solder paste? Is the decision based on gut feel or hard data?This paper presents a process for evaluating solder pastes using a variety of methods. These methods are quick to run and are challenging, revealing the strengths and weaknesses of solder pastes. Methods detailed in this paper include: print volume, stencil life, response to pause, open time, tack force over time, wetting, solder balling, graping, voiding, accelerated aging, and others.
Technical Library | 2013-07-18 12:12:40.0
Lead-free nanosolders have shown promise in nanowire and nanoelectronics assembly. Among various important parameters, melting is the most fundamental property affecting the assembly process. Here we report that the melting behavior of tin and tin/silver nanowires and nanorods can be significantly affected by the surface oxide of nanosolders.
Department of Chemical Engineering, University of Massachusetts
Technical Library | 2013-01-17 15:37:21.0
A problem exists with electroless nickel / immersion gold (ENIG) surface finish on some pads, on some boards, that causes the solder joint to separate from the nickel surface, causing an open. The solder has wet and dissolved the gold. A weak tin to nickel intermetallic bond initially occurs, but the intermetallic bond cracks and separates when put under stress. Since the electroless nickel / immersion gold finish performs satisfactory in most applications, there had to be some area within the current chemistry process window that was satisfactory. The problem has been described as a 'BGA Black Pad Problem' or by HP as an 'Interfacial Fracture of BGA Packages…'[1]. A 24 variable experiment using three different chemistries was conducted during the ITRI (Interconnect Technology Research Institute) ENIG Project, Round 1, to investigate what process parameters of the chemical matrix were potentially satisfactory to use and which process parameters of the chemical matrix need to be avoided. The ITRI ENIG Project has completed Round 1 of testing and is now in the process of Round 2 TV (Test Vehicle) build.
Technical Library | 1999-05-06 13:38:45.0
This paper traces the key steps that led to the invention of the integrated circuit (IC). The first part of this paper reviews the steady improvements in the performance and fabrication of single transistors in the decade after the Bell Labs breakthrough work in 1947. It sketches the various developments needed to produce a practical IC. In addition, the more advanced processes such as diffusion, oxide masking, photolithography, and epitaxy, which culminated in the planar process, are summarized.
Technical Library | 2021-12-29 19:52:50.0
Medtronic seeks to quantify the thermal aging limits of electroless Ni-electroless Pd-immersion Au (ENEPIG) surface finishes to determine how aggressive the silicon burn-in process can be without loss of solderability. Silicon burn-in (power testing at elevated temperature) is used to eliminate early field failures, critical for device reliability. Thermal aging due to burn-in or annealing causes Ni and Pd diffusion to and oxidation on the surface. Surface oxides limit wetting of the PbSn solder, affecting electrical connectivity of components soldered afterburn-in. Isothermal aging of two ENEPIG surface finishes was performed at 75°C-150°C for 100 hrs-1500hrs to test the thermal aging limits and identify how loss of solderability occurs.
Technical Library | 1999-05-07 08:48:52.0
This paper describes how the quality and reliability of Intel's products are designed, measured, modeled, and maintained. Four main reliability topics: ESD protection, electromigration, gate oxide wearout, and the modeling and management of mechanical stresses are discussed. Based on an analysis of the reliability implications of device scaling, we show how these four topics are of prime importance to component reliability...
Technical Library | 2018-05-23 12:12:43.0
Driven by miniaturization, cost reduction and tighter requirements for electrical and thermal performance, the use of lead-frame based bottom-termination components (LF-BTC) as small-outline no-leads (SON), quad-flat no leads (QFN) packages etc., is increasing. However, a major distractor for the use of such packages in high-reliability applications has been the lack of a visible solder (toe) fillet on the edge surface of the pins: because the post-package assembly singulation process typically leaves bare copper leadframe at the singulation edge, which is not protected against oxidation and thus does not easily solder-wet, a solder fillet (toe fillet) does not generally develop.
Technical Library | 2014-07-24 16:26:34.0
Wire bonding a die to a package has traditionally been performed using either aluminum or gold wire. Gold wire provides the ability to use a ball and stitch process. This technique provides more control over loop height and bond placement. The drawback has been the increasing cost of the gold wire. Lower cost Al wire has been used for wedge-wedge bonds but these are not as versatile for complex package assembly. The use of copper wire for ball-stitch bonding has been proposed and recently implemented in high volume to solve the cost issues with gold. As one would expect, bonding with copper is not as forgiving as with gold mainly due to oxide growth and hardness differences. This paper will examine the common failure mechanisms that one might experience when implementing this new technology.
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