Technical Library | 2007-04-05 13:48:50.0
Recently a large global player approached us with a problem. They needed an initial assembly solution for brand new components. Their boards and CSP specimens could not safely be soldered due to wetting problems at the solder joints.
Technical Library | 2010-06-10 21:01:48.0
This paper researches the effectiveness of the R.O.S.E. cleanliness testing process for dissolving and measuring ionic contaminants from boards soldered with no-clean and lead-free flux technologies.
Technical Library | 2011-08-11 20:06:48.0
(Proceedings of the World Congress on Engineering 2011) A Printed Circuit Board (PCB) consists of circuit with electronic components mounted on surface. There are three main steps involved in manufacturing process, where the inspection of PCB is necessar
Sant Longowal Institute of Engineering and Technology (SLIET)
Technical Library | 2012-03-22 20:40:01.0
Miniaturization continues to be a driving force in both integrated circuit packaging and printed circuit board laminate technology. In addition to decreasing component pitch (lead to lead spacing), utilization of the vertical space by stacking packages ha
Technical Library | 2012-09-13 20:45:17.0
First published in the 2012 IPC APEX EXPO technical conference proceedings. Prior to committing production boards to vapor phase soldering, we performed an evaluation to assess reliability and evaluate the vacuum soldering option. The reliability of vapor
Technical Library | 2016-06-16 15:29:31.0
Embedding components within the PC board structure is not a new concept. Until recently, however, most embedded component PC board applications adapted only passive elements. The early component forming processes relied on resistive inks and films to enable embedding of resistor and capacitors elements. Although these forming methods remain viable, many companies are choosing to place very thin discrete passive components and semiconductor die elements within the PC board layering structure. In addition to improving the products performance, companies have found that by reducing the component population on the PC board's surface, board level assembly is less complex and the PC board can be made smaller, The smaller substrate, even when more complex, often results in lower cost. Although size and cost reductions are significant attributes, the closer coupling of key elements can also contribute to improving functional performance.This paper focuses on six basic embedded component structure designs described in IPC-7092.
Technical Library | 2018-08-22 14:05:42.0
Glass substrates are emerging as a key alternative to silicon and conventional organic substrates for high-density and high-performance systems due to their outstanding dimensional stability, enabling sub-5-µm lithographic design rules, excellent electrical performance, and unique mechanical properties, key in achieving board-level reliability at body sizes larger than 15 × 15 mm2. This paper describes the first demonstration of the board-level reliability of such large, ultrathin glass ball grid array (BGA) packages directly mounted onto a system board, considering both their thermal cycling and drop-test performances.
Technical Library | 2010-03-30 21:51:23.0
This paper presents the drop test reliability results for edge-bonded 0.5mm pitch lead-free chip scale packages (CSPs) on a standard JEDEC drop reliability test board.
Technical Library | 2015-11-25 14:15:12.0
In this study various printed circuit board surface finishes were evaluated, including: organic solderability preservative (OSP), plasma finish (PF), immersion silver (IAg), electroless nickel / immersion silver (ENIS), electroless nickel / immersion gold hi-phosphorus (ENIG Hi-P), and electroless nickel / electroless palladium / immersion gold (ENEPIG). To verify the performance of PF as a post-treatment option, it was added to IAg, ENIG Hi-P, and ENEPIG to compare with non-treated. A total of nine groups of PCB were evaluated. Each group contains 30 boards, with the exception on ENIS where only 8 boards were available.
Technical Library | 2021-12-21 23:01:30.0
High density PWB (printed wiring board) with microvia technology is required for implementation of high density and high I/O area array packages (AAP). COTS (commercial off-the-shelf) AAP packaging technologies in high reliability versions with 1.27 mm pitch are now being considered for use in a number of NASA systems including the Space Shuttle and Mars Rovers. NASA functional system designs are requiring ever more denser AAP packages and board features, making board microvia technology very attractive for effectively routing a large number of package inputs/outputs.
