Technical Library | 2019-05-24 09:22:59.0
There is a smaller process window and a much narrower margin of error when creating and using lead-free reflow profiles for surface mount parts on printed circuit boards (PCBs). Solder balls, dewetting, tombstones, voids, and head-on-pillow problems will occur much more frequently because lead-free alloys behave differently than eutectic pastes. Problems are compounded due to the extra heat necessary for some lead-free pastes to reach their melting points.
Technical Library | 2017-02-01 02:20:42.0
BGA Rework Course encompasses the skills necessary to perform rework of electronic printed circuit boards to include PBGA and CBGA technologies. There should be 'one-stop' solution, that offers a wide range of ball grid array rework and repair services.
Technical Library | 2008-10-29 18:45:53.0
Growing demand for compact, multi-function electronics products has accelerated component miniaturization and high-density placement, creating new challenges for the electronics manufacturing industry. It is no longer adequate to simply place parts accurately per a pre-defined CAD assembly program because solder paste alignment errors are increasing for numerous reasons. The solution to this problem is a system in which the placement machine can automatically detect and compensate for misalignment of the solder paste to produce high-quality boards regardless of the process errors beforehand.
Technical Library | 2009-12-14 20:24:19.0
In the lead-free era, thermal profiling has a critical role in the SMT assembly process. We discuss the profiling, tools, practical issues, and inspection methods of golden boards, and related tools. As the process window narrows, profiling equipment and/or thermocouple (TC) errors must be taken into consideration. In addition, the accuracy and attachment method of the thermocouple will significantly impact critical assemblies.
Technical Library | 2019-08-15 13:31:52.0
Cracks in ceramic chip capacitors can be introduced at any process step during surface mount assembly. Thermal shock has become a "pat" answer for all of these cracks, but about 75 to 80% originate from other sources. These sources include pick and place machine centering jaws, vacuum pick up bit, board depanelization, unwarping boards after soldering, test fixtures, connector insulation, final assembly, as well as defective components. Each source has a unique signature in the type of crack that it develops so that each can be identified as the source of error.
Technical Library | 2024-04-29 21:39:52.0
In this paper, we develop and put into practice an Automatic Optical Inspection (AOI) system based on machine vision to check the holes on a printed circuit board (PCB). We incorporate the hardware and software. For the hardware part, we combine a PC, the three-axis positioning system, a lighting device and CCD cameras. For the software part, we utilize image registration, image segmentation, drill numbering, drill contrast, and defect displays to achieve this system. Results indicated that an accuracy of 5µm could be achieved in errors of the PCB holes allowing comparisons to be made. This is significant in inspecting the missing, the multi-hole and the incorrect location of the holes. However, previous work only focusses on one or other feature of the holes. Our research is able to assess multiple features: missing holes, incorrectly located holes and excessive holes. Equally, our results could be displayed as a bar chart and target plot. This has not been achieved before. These displays help users analyze the causes of errors and immediately correct the problems. Additionally, this AOI system is valuable for checking a large number of holes and finding out the defective ones on a PCB. Meanwhile, we apply a 0.1mm image resolution which is better than others used in industry. We set a detecting standard based on 2mm diameter of circles to diagnose the quality of the holes within 10 seconds.
Technical Library | 2020-12-16 18:50:42.0
System operating speeds continue to increase as a function of the consumer demand for such technologies as faster Internet connectivity, video on demand, and mobile communications technology. As a result, new high performance PCB substrates have emerged to address signal integrity issues at higher operating frequencies. These are commonly called low Dk and/or low loss (Df) materials. The published "typical" values found on a product data sheet provide limited information, usually a single construction and resin content, and are derived from a wide range of test methods and test sample configurations. A printed circuit board designer or front end application engineer must be aware that making a design decision based on the limited information found on a product data sheet can lead to errors which can delay a product launch or increase the assembled PCB cost. The purpose of this paper is to highlight critical selection factors that go beyond a typical product data sheet and explain how these factors must be considered when selecting materials for high speed applications
Technical Library | 2019-10-24 06:29:59.0
Making your novel electronic item design ready for mass fabrication and printed circuit board assembly consists of a lot of steps as well as risks. I will provide a few recommendations about how to neglect pricey errors and how to reduce the time to promote your novel item designs. You can hire printed circuit board assembly services for this. As soon as you have accomplished your product as well as printed circuit board design, you wish to get started developing prototypes prior to you commit to big fabrication volume. A lot of design software packages, for instance, PCB layout design software, as well as an industrial design software program, possess simulation potentials incorporated. Carrying out a simulation facilitates curtailing numerous design mistakes prior to the first prototype is developed. In case you are developing an intrusive item, you might desire to think about a modular design wherein all of the chief functionalities are situated in individual modules. All through your testing, you could then swap modules that don’t cater to the design limits. Spinning individual modules would be swifter and more cost-effective in comparison to spinning a complete design. Counting on the design intricacy, you can mull over manually mounting printed circuit board elements to bank dollars. Nonetheless, for medium to big intricacy this procedure likely to be very time taking, typically in case you wish to create numerous prototypes. Hence it makes sense thinking about a contract manufacturer for the assembly. Whilst running miniature quantity fabrication runs, the fabrication setup expenditure will usually control the by and large prototype constructs expenditure. Whilst seeking a subcontractor, it is finest to choose a vendor that focuses on prototype builds to reduce the cost. Prototype printed circuit board fabricators characteristically join the circuit boards of a number of clients which efficiently shares the setup expenditure in the midst of some customers. The disadvantage is that you would characteristically only be able to want among numerous standard printed circuit board material thicknesses as well as sizes. Apart from choosing a supplier with low setup expenditure, choosing a firm that would moreover be capable to manage your whole fabrication runs curtails mistakes because switching fabricators have the chance of errors owing to a specific supplier interpreting fabrication design data in a different way. This manner your design is already translated into the particular machine data that implies little or no setup expenditure for your final fabrication. A few PCB manufacturers also provide printed circuit board design services that are awesome plus if you do not possess experience with the design. Moreover, these vendors would be capable to help you in case there are issues with your design folders and be capable to detect issues prior to the fabrication.
Technical Library | 2021-07-20 20:02:29.0
During the manufacturing of printed circuit boards (PCBs) for a Flight Project, it was found that a European manufacturer was building its boards to a European standard that had no requirement for copper wrap on the vias. The amount of copper wrap that was measured on coupons from the panel containing the boards of interest was less than the amount specified in IPC-6012 Rev B, Class 3. To help determine the reliability and usability of the boards, three sets of tests and a simulation were run. The test results, along with results of simulation and destructive physical analysis, are presented in this paper. The first experiment involved subjecting coupons from the panels supplied by the European manufacturer to thermal cycling. After 17 000 cycles, the test was stopped with no failures. A second set of accelerated tests involved comparing the thermal fatigue life of test samples made from FR4 and polyimide with varying amounts of copper wrap. Again, the testing did not reveal any failures. The third test involved using interconnect stress test coupons with through-hole vias and blind vias that were subjected to elevated temperatures to accelerate fatigue failures. While there were failures, as expected, the failures were at barrel cracks. In addition to the experiments, this paper also discusses the results of finite-element analysis using simulation software that was used to model plated-through holes under thermal stress using a steady-state analysis, also showing the main failure mode was barrel cracking. The tests show that although copper wrap was sought as a better alternative to butt joints between barrel plating and copper foil layers, manufacturability remains challenging and attempts to meet the requirements often result in features that reduce the reliability of the boards. Experimental and simulation work discussed in this paper indicate that the standard requirements for copper wrap are not contributing to the overall board reliability, although it should be added that a design with a butt joint is going to be a higher risk than a reduced copper wrap design. The study further shows that procurement requirements for wrap plating thickness from Class 3 to Class 2 would pose little risk to reliability (minimum 5 μm/0.197 mil for all via types).Experimental results corroborated by modeling indicate that the stress maxima are internal to the barrels rather than at the wrap location. In fact, the existence of Cu wrap was determined to have no appreciable effect on reliability.
Technical Library | 2020-07-08 20:05:59.0
There is a compelling need for functional testing of high-speed input/output signals on circuit boards ranging from 1 gigabit per second (Gbps) to several hundred Gbps. While manufacturing tests such as Automatic Optical Inspection (AOI) and In-Circuit Test (ICT) are useful in identifying catastrophic defects, most high-speed signals require more scrutiny for failure modes that arise due to high-speed conditions, such as jitter. Functional ATE is seldom fast enough to measure high-speed signals and interpret results automatically. Additionally, to measure these adverse effects it is necessary to have the tester connections very close to the unit under test (UUT) as lead wires connecting the instruments can distort the signal. The solution we describe here involves the use of a field programmable gate array (FPGA) to implement the test instrument called a synthetic instrument (SI). SIs can be designed using VHDL or Verilog descriptions and "synthesized" into an FPGA. A variety of general-purpose instruments, such as signal generators, voltmeters, waveform analyzers can thus be synthesized, but the FPGA approach need not be limited to instruments with traditional instrument equivalents. Rather, more complex and peculiar test functions that pertain to high-speed I/O applications, such as bit error rate tests, SerDes tests, even USB 3.0 (running at 5 Gbps) protocol tests can be programmed and synthesized within an FPGA. By using specific-purpose test mechanisms for high-speed I/O the test engineer can reduce test development time. The synthetic instruments as well as the tests themselves can find applications in several UUTs. In some cases, the same test can be reused without any alteration. For example, a USB 3.0 bus is ubiquitous, and a test aimed at fault detection and diagnoses can be used as part of the test of any UUT that uses this bus. Additionally, parts of the test set may be reused for testing another high-speed I/O. It is reasonable to utilize some of the test routines used in a USB 3.0 test, in the development of a USB 3.1 (running at 10 Gbps), even if the latter has substantial differences in protocol. Many of the SI developed for one protocol can be reused as is, while other SIs may need to undergo modifications before reuse. The modifications will likely take less time and effort than starting from scratch. This paper illustrates an example of high-speed I/O testing, generalizes failure modes that are likely to occur in high-speed I/O, and offers a strategy for testing them with SIs within FPGAs. This strategy offers several advantages besides reusability, including tester proximity to the UUT, test modularization, standardization approaching an ATE-agnostic test development process, overcoming physical limitations of general-purpose test instruments, and utilization of specific-purpose test instruments. Additionally, test instrument obsolescence can be overcome by upgrading to ever-faster and larger FPGAs without losing any previously developed design effort. With SIs and tests scalable and upward compatible, the test engineer need not start test development for high-speed I/O from scratch, which will substantially reduce time and effort.
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