Technical Library: bonding pad (Page 1 of 2)

NSOP Reduction for QFN RFIC Packages

Technical Library | 2017-08-31 13:43:48.0

Wire bonded packages using conventional copper leadframe have been used in industry for quite some time. The growth of portable and wireless products is driving the miniaturization of packages resulting in the development of many types of thin form factor packages and cost effective assembly processes. Proper optimization of wire bond parameters and machine settings are essential for good yields. Wire bond process can generate a variety of defects such as lifted bond, cracked metallization, poor intermetallic etc. NSOP – non-stick on pad is a defect in wire bonding which can affect front end assembly yields. In this condition, the imprint of the bond is left on the bond pad without the wire being attached. NSOP failures are costly as the entire device is rejected if there is one such failure on any bond pad. The paper presents some of the failure modes observed and the efforts to address NSOP reduction

Peregrine Semiconductor

Approaches to Overcome Nodules and Scratches on Wire Bondable Plating on PCBs

Technical Library | 2020-08-27 01:22:45.0

Initially adopted internal specifications for acceptance of printed circuit boards (PCBs) used for wire bonding was that there were no nodules or scratches allowed on the wirebond pads when inspected under 20X magnification. The nodules and scratches were not defined by measurable dimensions and were considered to be unacceptable if there was any sign of a visual blemish on wire-bondable features. Analysis of the yield at a PCB manufacturer monitored monthly for over two years indicated that the target yield could not be achieved, and the main reasons for yield loss were due to nodules and scratches on the wirebonding pads. The PCB manufacturer attempted to eliminate nodules and scratches. First, a light-scrubbing step was added after electroless copper plating to remove any co-deposited fine particles that acted as a seed for nodules at the time of copper plating. Then, the electrolytic copper plating tank was emptied, fully cleaned, and filtered to eliminate the possibility of co-deposited particles in the electroplating process. Both actions greatly reduced the density of the nodules but did not fully eliminate them. Even though there was only one nodule on any wire-bonding pad, the board was still considered a reject. To reduce scratches on wirebonding pads, the PCB manufacturer utilized foam trays after routing the boards so that they did not make direct contact with other boards. This action significantly reduced the scratches on wire-bonding pads, even though some isolated scratches still appeared from time to time, which caused the boards to be rejected. Even with these significant improvements, the target yield remained unachievable. Another approach was then taken to consider if wire bonding could be successfully performed over nodules and scratches and if there was a dimensional threshold where wire bonding could be successful. A gold ball bonding process called either stand-off-stitch bonding (SSB) or ball-stitch-on-ball bonding (BSOB) was used to determine the effects of nodules and scratches on wire bonds. The dimension of nodules, including height, and the size of scratches, including width, were measured before wire bonding. Wire bonding was then performed directly on various sizes of nodules and scratches on the bonding pad, and the evaluation of wire bonds was conducted using wire pull tests before and after reliability testing. Based on the results of the wire-bonding evaluation, the internal specification for nodules and scratches for wirebondable PCBs was modified to allow nodules and scratches with a certain height and a width limitation compared to initially adopted internal specifications of no nodules and no scratches. Such an approach resulted in improved yield at the PCB manufacturer.

Teledyne DALSA

Strategies for Designing Microwave Multilayer Printed Circuit Boards Using Stripline Structures

Technical Library | 2010-06-03 22:23:03.0

Strategies for successful design and manufacture of microwave multilayer printed circuit boards. All aspects from pad registration, dimensional stability, impedance fluctuation, fusion bonding, thermal ageing, z-axis expansion, reliability, to Young's mod

Taconic

Challenges on ENEPIG Finished PCBs: Gold Ball Bonding and Pad Metal Lift

Technical Library | 2017-09-07 13:56:11.0

As a surface finish for PCBs, Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG) was selected over Electroless Nickel/Immersion Gold (ENIG) for CMOS image sensor applications with both surface mount technology (SMT) and gold ball bonding processes in mind based on the research available on-line. Challenges in the wire bonding process on ENEPIG with regards to bondability and other plating related issues are summarized.

Teledyne DALSA

Packaging Technology and Design Challenge for Fine Pitch Micro-Bump Cu-Pillar and BOT (Direct Bond on Substrate-Trace) Using TCNCP

Technical Library | 2015-12-02 18:32:50.0

(Thermal Compression with Non-Conductive Paste Underfill) Method.The companies writing this paper have jointly developed Copper (Cu) Pillar micro-bump and TCNCP(Thermal Compression with Non-Conductive Paste) technology over the last two+ years. The Cu Pillar micro-bump and TCNCP is one of the platform technologies, which is essentially required for 2.5D/3D chip stacking as well as cost effective SFF (small form factor) package enablement.Although the baseline packaging process methodology for a normal pad pitch (i.e. inline 50μm) within smaller chip size (i.e. 100 mm2) has been established and are in use for HVM production, there are several challenges to be addressed for further development for commercialization of finer bump pitch with larger die (i.e. ≤50μm tri-tier bond pad with the die larger than 400mm2).This paper will address the key challenges of each field, such as the Cu trace design on a substrate for robust micro-joint reliability, TCNCP technology, and substrate technology (i.e. structure, surface finish). Technical recommendations based on the lessons learned from a series of process experimentation will be provided, as well. Finally, this technology has been used for the successful launching of the company FPGA products with SFF packaging technology.

Altera Corporation

Fine Pitch Cu Pillar with Bond on Lead (BOL) Assembly Challenges for High Performance Flip Chip Package

Technical Library | 2018-01-17 22:47:02.0

Fine pitch copper (Cu) Pillar bump has been growing adoption in high performance and low-cost flip chip packages. Higher input/output (I/O) density and very fine pitch requirements are driving very small feature sizes such as small bump on a narrow pad or bond-on-lead (BOL) interconnection, while higher performance requirements are driving increased current densities, thus assembling such packages using a standard mass reflow (MR) process and maintaining its performance is a real and serious challenge. (...) In this study a comprehensive finding on the assembly challenges, package design, and reliability data will be published. Originally published in the SMTA International 2016

STATS ChipPAC Inc

Solder Joint Reliability Under Realistic Service Conditions

Technical Library | 2014-10-30 01:48:43.0

The ultimate life of a microelectronics component is often limited by failure of a solder joint due to crack growth through the laminate under a contact pad (cratering), through the intermetallic bond to the pad, or through the solder itself. Whatever the failure mode proper assessments or even relative comparisons of life in service are not possible based on accelerated testing with fixed amplitudes, or random vibration testing, alone. Effects of thermal cycling enhanced precipitate coarsening on the deformation properties can be accounted for by microstructurally adaptive constitutive relations, but separate effects on the rate of recrystallization lead to a break-down in common damage accumulation laws such as Miner's rule. Isothermal cycling of individual solder joints revealed additional effects of amplitude variations on the deformation properties that cannot currently be accounted for directly. We propose a practical modification to Miner's rule for solder failure to circumvent this problem. Testing of individual solder pads, eliminating effects of the solder properties, still showed variations in cycling amplitude to systematically reduce subsequent acceleration factors for solder pad cratering. General trends, anticipated consequences and remaining research needs are discussed

Universal Instruments Corporation

Investigation of Impacts on Printed Circuit Board Laminated Composites Caused by Surface Finish Application

Technical Library | 2021-12-29 19:37:20.0

The purpose of this study was to compare the strength of the bond between resin and glass cloth for various composites (laminates) and its dependence on utilized soldering pad surface finishes. Moreover, the impact of surface finish application on the thermomechanical properties of the composites was evaluated. Three different laminates with various thermal endurances were included in the study. Soldering pads were covered with OSP and HASL surface finishes. The strength of the cohesion of the resin upper layer was examined utilizing a newly established method designed for pulling tests.

Czech Technical University in Prague

Surface Treatment Enabling Low Temperature Soldering to Aluminum

Technical Library | 2020-07-29 19:58:48.0

The majority of flexible circuits are made by patterning copper metal that is laminated to a flexible substrate, which is usually polyimide film of varying thickness. An increasingly popular method to meet the need for lower cost circuitry is the use of aluminum on Polyester (Al-PET) substrates. This material is gaining popularity and has found wide use in RFID tags, low cost LED lighting and other single-layer circuits. However, both aluminum and PET have their own constraints and require special processing to make finished circuits. Aluminum is not easy to solder components to at low temperatures and PET cannot withstand high temperatures. Soldering to these materials requires either an additional surface treatment or the use of conductive epoxy to attach components. Surface treatment of aluminum includes the likes of Electroless Nickel Immersion Gold plating (ENIG), which is extensive wet-chemistry and cost-prohibitive for mass adoption. Conductive adhesives, including Anisotropic Conductive Paste (ACP), are another alternate to soldering components. These result in component substrate interfaces that are inferior to conventional solders in terms of performance and reliability. An advanced surface treatment technology will be presented that addresses all these constraints. Once applied on Aluminum surfaces using conventional printing techniques such as screen, stencil, etc., it is cured thermally in a convection oven at low temperatures. This surface treatment is non-conductive. To attach a component, a solder bump on the component or solder printed on the treated pad is needed before placing the component. The Aluminum circuit will pass through a reflow oven, as is commonly done in PCB manufacturing. This allows for the formation of a true metal to metal bond between the solder and the aluminum on the pads. This process paves the way for large scale, low cost manufacturing of Al-PET circuits. We will also discuss details of the process used to make functional aluminum circuits, study the resultant solder-aluminum bond, shear results and SEM/ EDS analysis.

Averatek Corporation

Solving the ENIG Black Pad Problem: An ITRI Report on Round 2

Technical Library | 2013-01-17 15:37:21.0

A problem exists with electroless nickel / immersion gold (ENIG) surface finish on some pads, on some boards, that causes the solder joint to separate from the nickel surface, causing an open. The solder has wet and dissolved the gold. A weak tin to nickel intermetallic bond initially occurs, but the intermetallic bond cracks and separates when put under stress. Since the electroless nickel / immersion gold finish performs satisfactory in most applications, there had to be some area within the current chemistry process window that was satisfactory. The problem has been described as a 'BGA Black Pad Problem' or by HP as an 'Interfacial Fracture of BGA Packages…'[1]. A 24 variable experiment using three different chemistries was conducted during the ITRI (Interconnect Technology Research Institute) ENIG Project, Round 1, to investigate what process parameters of the chemical matrix were potentially satisfactory to use and which process parameters of the chemical matrix need to be avoided. The ITRI ENIG Project has completed Round 1 of testing and is now in the process of Round 2 TV (Test Vehicle) build.

Celestica Corporation

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