Technical Library | 2019-05-29 23:10:30.0
There are times when a PCB prototype needs to be built quickly to test out a design. In such cases where it is known early on that there will be multiple iterations or that a "one and done" assembly will be made that there will be some SMT assemblers who choose to hand print solder paste onto the board using a "frameless" stencil. In such cases where hand printing is used, the consistency of the printing technique has typically been in question. Furthermore, the effectiveness of both the nanocoatings as well as the higher end stainless steel materials, which have been heretofore studied in controlled printing environments, will be evaluated for their impact on the hand printing process.The purpose of the study was to determine the effectiveness of select nanocoating materials as well as certain high end stainless steel stencil materials as they relate to the manual SMT printing process. A variety of nanocoatings were applied to SMT metal stencils and solder paste volume measurements were taken to compare the effectiveness.
Technical Library | 2007-08-23 14:30:03.0
The complexity and programmability of modern embedded boards means that knowledge built up during debugging and testing must be regarded as Intellectual Property (IP) and therefore preserved. But many of the processes and tools used today do not provide a means to preserve or pass on this IP, and thereby forego valuable opportunities to save time and improve quality during subsequent stages of product development.
Technical Library | 2018-06-20 13:11:57.0
Manufacturers test to ensure that the product is built correctly. Shorts, opens, wrong or incorrectly inserted components, even catastrophically faulty components need to be flagged, found and repaired. When all such faults are removed, however, functional faults may still exist at normal operating speed, or even at lower speeds. Functional board test (FBT) is still required, a process that still relies on test engineers’ understanding of circuit functionality and manually developed test procedures. While functional automatic test equipment (ATE) has been reduced considerably in price, FBT test costs have not been arrested. In fact, FBT is a huge undertaking that can take several weeks or months of test engineering development, unacceptably stretching time to market. The alternative, of selling products that have not undergone comprehensive FBT is equally, if not more, intolerable.
Technical Library | 2008-02-26 15:02:19.0
More and more chip packages need multi-GHz RF structures to meet their performance targets. The ideal chip package needs to combine RF features with Digital features for these applications. They drive low-loss, controlled impedance transmission lines, flexibility in assigned signal and power layers, and clearances of various shapes in power layers. Building these features in a chip package is difficult without making the stack-up very thick or compromising the reliability of the product. In the present paper, we have designed and built a flip-chip package test vehicle (TV) to make new RF structures, using Z-axis interconnection (Zinterconnect) building blocks.
Technical Library | 2016-04-14 13:49:44.0
A system level test, usually built-in test (BIT), determines that one or more subsystems are faulty. These subsystems sent to the depot or factory repair facility, called units under test (UUTs) often pass that test, an event we call No-Fault-Found (NFF). With more-and more electronics monitored by BIT, it is more likely that an intermittent glitch will trigger a call for a maintenance action resulting in NFF. NFFs are often confused with false alarm (FA), cannot duplicate (CNDs)or retest OK (RTOK) events. NFFs at the depot are caused by FAs, CNDs, RTOKs as well as a number of other complications. Attempting to repair NFF scan waste precious resources, compromise confidence in the product, create customer dissatisfaction, and the repair quality remains a mystery. The problem is compounded by previous work showing that most failure indications calling for repair action at the system level are invalid. NFFs can be caused by real failures or may be a result of system level false alarms. Understanding the cause of the problem may help us distinguish between units under test (UUTs) that we can repair and those that we cannot. In calculating the true cost of repair we must account for wasted effort in attempting to repair unrepairable UUTs.This paper will shed some light on this trade-off. Finally, we will explore approaches for dealing with the NFF issue in a cost effective manner.
Technical Library | 2016-06-23 13:24:56.0
Proper assembly of components is critical in the manufacturing industry as it affects functionality and reliability. In a heat sink assembly, a detailed manual process is often utilized. However, an automated fixture is used whenever applicable.This paper will illustrate the use of strain gauge testing and Finite Element Analysis (FEA) as a simulation tool to evaluate and optimize the heat sink assembly process by manual and automated methods. Several PCBAs in the production line were subjected to the manual and automated assembly process. Strain gauge testing was performed and FEA models were built and run. Results were compared with the goal of improving the FEA model. The updated FEA model will be used in simulating different conditions in assembly. Proposed improvement solutions to some issues can also be verified through FEA.
Technical Library | 2018-12-12 22:20:22.0
Numerous 3D stack packaging technologies have been implemented by industry for use in microelectronics memory applications. This paper presents a reliability evaluation of a particular package-on-package (PoP) that offers a reduction in overall PCB board area requirements while allowing for increases in functionality. It utilizes standard, readily available device packaging methods in which high-density packaging is achieved by: (1) using standard "packaged" memory devices, (2) using standard 3-dimensional (3-D) interconnect assembly. The stacking approach provides a high level of functional integration in well-established and already functionally tested packages. The stack packages are built from TSOP packages with 48 leads, stacked either 2-high or 4-high, and integrated into a single dual-flat-no-lead (DFN) package.
Technical Library | 2011-04-21 18:55:48.0
Switching systems, and in particular matrices are a key part of many tests systems, they allow a single core set of test equipment to be connected to the UUT, saving the cost of duplicating test equipment. That places the switching matrix in a very vulner
Technical Library | 2021-03-24 01:34:35.0
In this article we propose a generic test script for real=time embedded software system testing, which has been applied to ATE (Automated Test Equipment). After a summary of the theory about embedded software automated test based on test script, the design philosophy and implementation details are described. We have chosen an ATE and integrated python interpreter into it.
Technical Library | 2016-05-13 11:44:16.0
The process of manufacturing and qualifying IC's consists of many steps while Temperature forcing systems play a crucial role in the final testing process. These environmental tests assure quality and reliability by stressing the device on one hand as well as helping to characterize and validate it on the other hand (making sure manufacturing outcome meets the design requirements). At later stages the temperature testing can support failure analysis effort and root cause analysis. AS common practice we are dealing with few different kinds of temperature forcing systems: Chambers, Thermal Stream systems and Direct Thermal Head systems. In this article I would like to focus on the practical aspects of utilizing Thermal Stream systems and Direct Thermal Head systems.
