Technical Library | 2019-05-31 14:19:24.0
ACI Technologies (ACI) characterized the reliability of surface mount RF components. The RF frequency band of interest was the X band (10.7 to 11.7GHz). A two pronged test for reliability of circuit card assemblies (CCA) was designed for both extreme thermal cycling and vibration. The rapid thermal cycling and extreme vibration testing simulates the total stress encountered by the assembly over the life of the product but accomplishes it in a relatively short period of time. In order to perform the reliability testing, a test vehicle consisting of a printed circuit board with test structures and components, was designed, fabricated, and assembled at ACI.
Technical Library | 2024-06-20 22:53:23.0
A leading electronic hearing device manufacturer reduced UV precise coating cycle time by 79% with advanced automation. A manual process of hand brushing UV coating onto components was replaced by an automated solution from Nordson to increase production volumes, improve quality, and reduce costs for this complex application. Download the paper to learn the details of the application.
Technical Library | 2020-09-02 14:34:23.0
Atomic layer deposition (ALD) is a process of creating coatings on a molecular layer by layer basis. Using an iterated sequence of self-saturating deposition cycles that are self-terminating, a single layer can be deposited at a time, allowing for highly uniform films with complete conformality. The composition of the film typically used for coating printed wiring boards (PWBs) is a high alumina (Al2O3) sequential deposition of alumina and titania capped with a corrosion protective titanium aluminate layer, most notably ALD-Cap from Sundew Technologies, LLC. Rework is a process of restoring an electronics assembly to full functionality to prolong equipment life and reduce the amount of scrap. The process typically involves:
Technical Library | 2012-12-17 22:05:22.0
Package on Package (PoP) has become a relatively common component being used in mobile electronics as it allows for saving space in the board layout due to the 3D package layout. To insure device reliability through drop tests and thermal cycling as well as for protecting proprietary programming of the device either one or both interconnect layers are typically underfilled. When underfill is applied to a PoP, or any component for that matter, there is a requirement that the board layout is such that there is room for an underfill reservoir so that the underfill material does not come in contact with surrounding components. The preferred method to dispensing the underfill material is through a jetting process that minimizes the wet out area of the fluid reservoir compared to traditional needle dispensing. To further minimize the wet out area multiple passes are used so that the material required to underfill the component is not dispensed at once requiring a greater wet out area. Dispensing the underfill material in multiple passes is an effective way to reduce the wet out area and decrease the distance that surrounding components can be placed, however, this comes with a process compromise of additional processing time in the underfill dispenser. The purpose of this paper is to provide insight to the inverse relationship that exists between the wet out area of the underfill reservoir and the production time for the underfill process.
Technical Library | 2024-08-05 16:57:08.0
A review of the factors involved in calculating the the cost of laser cutting and how laser cutting time is also calculated.
Technical Library | 2006-05-13 13:07:53.0
This Excel Spreadsheet calculates the Wave Solder Contact Time automatically with given main Solder Wave width and Conveyor Speed. There is one chart where conveyor speed is expressed in meters/min and in another where it is expressed in feet/minute.
Technical Library | 2021-07-28 18:35:13.0
The performance of electronic components is compromised by factors such as bubbles in the potting medium. Increasing numbers of applications – particularly in the automotive and electronics industries – therefore require completely bubble-free dispensing methods. This is where potting in a vacuum comes into focus. The widespread school of thought about this technology is that it is too complicated, too expensive and too slow. But a closer look shows that this view is incorrect. This is a mastered technology. As for costs, the calculation basis is key, since usually the potting and vacuum method is only considered after the required potting quality cannot be achieved reliably any other way. Under total cost of ownership assessments, higher system costs no longer play a key role, since component failure would result in much higher subsequent costs. And now there are proven solutions for high production volumes and/or shorter cycle times. This whitepaper explains when potting in a vacuum is ideal for your projects and what to be aware of.
Technical Library | 2024-07-24 00:51:44.0
A blade server system (BSS) utilizes voltage regulator modules (VRMs), in the form of quad flat no-lead (QFN) devices, to provide power distribution to various components on the system board. Depending on the power requirements of the circuit, these VRMs can be mounted as single devices or banked together. In addition, the power density of the VRM can be high enough to warrant heat dissipation through the use of a heat sink. Typically, at field conditions (FCs), the BSS are powered on and off up to four times per day, with their ambient temperature cycling between 258C and 808C. This cyclical temperature gradient drives inelastic strain in the solder joints due to the coefficient of thermal expansion (CTE) mismatch between the QFN and the circuit card. In addition, the heat sink, coupled with the QFN and the circuit card, can induce additional inelastic solder joint strain, resulting in early solder joint fatigue failure. To understand the effect of the heat sink mounting, a FEM (finite element model of four QFNs mounted to a BSS circuit card was developed. The model was exercised to calculate the maximum strain energy in a critical joint due to cyclic strain, and the results were compared for a QFN with and without a heat sink. It was determined that the presence of the heat sink did contribute to higher strain energy and therefore could lead to earlier joint failure. Although the presence of the heat sink is required, careful design of the mounting should be employed to provide lateral slip, essentially decoupling the heat sink from the QFN joint strain. Details of the modeling and results, along with DIC (digital image correlation) measurements of heat sink lateral slip, are presented.
Technical Library | 2020-12-10 15:49:40.0
Electronic assemblies should have longer and longer service life. Today there are partially demanded 20 years of functional capability for electronics for automotive application. On the other hand, smaller components, such as resistors of size 0201, are able to endure an increasing number of thermal cycles until fail of solder joints, so these are tested sometimes up to 4000 cycles. But testing until the end of life is essential for the determination of failure rates and the prognosis of reliability. Such tests require a lot of time, but this is often not available in developing of new modules. A further acceleration by higher cycle temperatures is usually not possible, because the materials are already operated at the upper limit of the load. However, the duration can be shortened by the use of liquids for passive tests, which allow faster temperature changes and shorter dwell times because of better heat transfer compared to air. The question is whether such tests lead to comparable results and what failure mechanisms are becoming effective. The same goes for active temperature cycles, in which the components itself are heated from inside and the substrate remains comparatively cold. This paper describes the various accelerated temperature cycling tests, compares and evaluates the related degradation of solder joints.
Technical Library | 2001-04-24 10:47:02.0
Board-level circuits today routinely run at speeds of 100 MHz or more and are composed of dozens of complex interacting VLSI components. To design such circuits in a timely and correct manner it is necessary to pay close attention to circuit timing early in the design cycle. At fast clock speeds, managing component and interconnect propagation delay becomes a key aspect of circuit design. It is imperative that the critical paths on a circuit and the slack available for interconnect delay consumption be identified early, and drive subsequent stages in the design flow.
