Technical Library: calculating solder area (Page 1 of 6)

THE EFFECT OF VACUUM REFLOW PROCESSING ON SOLDER JOINT VOIDING AND THERMAL FATIGUE RELIABILITY

Technical Library | 2023-01-17 17:19:44.0

A test program was developed to evaluate the effectiveness of vacuum reflow processing on solder joint voiding and subsequent thermal cycling performance. Area array package test vehicles were assembled using conventional reflow processing and a solder paste that generated substantial void content in the solder joints. Half of the population of test vehicles then were re-processed (reflowed) using vacuum reflow. Transmission x-ray inspection showed a significant reduction in solder voiding after vacuum processing. The solder attachment reliability of the conventional and vacuum reflowed test vehicles was characterized and compared using two different accelerated thermal cycling profiles. The thermal cycling results are discussed in terms of the general impact of voiding on solder thermal fatigue reliability, results from the open literature, and the evolving industry standards for solder voiding. Recommendations are made for further work based on other void reduction methods and additional reliability studies.

Heller Industries Inc.

Void Reduction in Bottom Terminated Components Using Vacuum Assisted Reflow

Technical Library | 2019-07-10 23:36:14.0

Pockets of gas, or voids, trapped in the solder interface between discrete power management devices and circuit assemblies are, unfortunately, excellent insulators, or barriers to thermal conductivity. This resistance to heat flow reduces the electrical efficiency of these devices, reducing battery life and expected functional life time of electronic assemblies. There is also a corresponding increase in current density (as the area for current conduction is reduced) that generates additional heat, further leading to performance degradation.

Heller Industries Inc.

Optimizing Reflowed Solder TIM (sTIMs) Processes for Emerging Heterogeneous Integrated Packages

Technical Library | 2023-01-17 17:12:33.0

Reflowed indium metal has for decades been the standard for solder thermal interface materials (solder TIMs or sTIMs) in most high-performance computing (HPC) TIM1 applications. The IEEE Heterogeneous Integration Thermal roadmap states that new thermal interface materials solutions must provide a path to the successful application of increased total-package die areas up to 100cm2. While GPU architectures are relatively isothermal during usage, CPU hotspots in complex heterogeneously-integrated modules will need to be able to handle heat flux hotspots up to 1000W/cm2 within the next two years. Indium and its alloys are used as reflowed solder thermal interface materials in both CPU and GPU "die to lid/heat spreader" (TIM1) applications. Their high bulk thermal conductivity and proven long-term reliability suit them well for extreme thermomechanical stresses. Voiding is the most important failure mode and has been studied by x-ray. The effects of surface pretreatment, pressure during reflow, solder flux type/fluxless processing, and preform design parameters, such as alloy type, are also examined. The paper includes data on both vacuum and pressure (autoclave) reflow of sTIMs, which is becoming necessary to meet upcoming requirements for ultralow voiding in some instances.

Heller Industries Inc.

Vacuum Fluxless Reflow Technology for Fine Pitch First Level Interconnect Bumping Applications

Technical Library | 2023-01-17 17:58:36.0

Heterogeneous integration has become an important performance enabler as high-performance computing (HPC) demands continue to rise. The focus to enable heterogeneous integration scaling is to push interconnect density limit with increased bandwidth and improved power efficiency. Many different advanced packaging architectures have been deployed to increase I/O wire / area density for higher data bandwidth requirements, and to enable more effective die disaggregation. Embedded Multi-die Interconnect Bridge (EMIB) technology is an advanced, cost-effective approach to in-package high density interconnect of heterogeneous chips, providing high density I/O, and controlled electrical interconnect paths between multiple dice in a package. In emerging architectures, it is required to scale down the EMIB die bump pitch in order to further increase the die-to-die (D2D) communication bandwidth. Aa a result, bump pitch scaling poses significant challenges in the plated solder bump reflow process, e.g., bump height / coplanarity control, solder wicking control, and bump void control. It's crucial to ensure a high-quality solder bump reflow process to meet the final product reliability requirements. In this paper, a combined formic acid based fluxless and vacuum assisted reflow process is developed for fine pitch plated solder bumping application. A high-volume production (HVM) ready tool has been developed for this process.

Heller Industries Inc.

New BGA Solder Mask Repair Technique Using Laser Cut Stencils

Technical Library | 2007-02-01 10:08:40.0

The increased replacement of high lead count SMT devices with BGAs and other high ball count area array packages has brought increased challenges to PCB rework and repair. Often solder mask areas surrounding BGA pad areas are damaged when components are removed.

BEST Inc.

BGA Rework. A Comparative Study of Selective Solder Paste Deposition For Area Array Packages

Technical Library | 2007-02-01 09:57:15.0

The rapid assimilation of Ball Grid Array (BGA) and other Area Array Package technology in the electronics industry is due to the fact that this package type allows for a greater I/O count in a smaller area while maintaining a pitch that allows for ease of manufacture.

BEST Inc.

Selective Solder Paste Deposition Reliability Test Results.

Technical Library | 2007-06-21 17:03:16.0

The rapid assimilation of Ball Grid Array (BGA) and other Area Array Package technology in the electronics industry is due to the fact that this package type allows for a greater I/O count in a smaller area while maintaining a pitch that allows for ease of manufacture (...) While there have been several studies comparing these two attachment methods, this study highlights the effect of rework technique on the electrical characteristics and reliability of reworked BGAs.

BEST Inc.

Pb-free solders: Comparison of different geometrical models in calculating of enthalpy of mixing of In-Sn-Zn ternary system.

Technical Library | 2014-05-22 17:10:37.0

In this paper, the general solution model of Chou has been used to predict the integral enthalpies of mixing of liquid In-Sn-Zn ternary alloys in five selected sections, xIn/xSn = 0.15/0.85, 0.34/0.66, 0.50/0.50, 0.67/0.33 and 0.85/0.15. The other traditional models such as Kohler, Muggianu, Toop and Hillert are also included in calculations. Comparison with literature data was done and showed reasonable agreement with Toop and Hillert asymmetric models.

Université Mohammed V-Agdal

Wave Solder Parameter Chart

Technical Library | 2006-05-13 13:07:53.0

This Excel Spreadsheet calculates the Wave Solder Contact Time automatically with given main Solder Wave width and Conveyor Speed. There is one chart where conveyor speed is expressed in meters/min and in another where it is expressed in feet/minute.

Jabil Circuit, Inc.

Estimating Recycling Return of Integrated Circuits Using Computer Vision on Printed Circuit Boards

Technical Library | 2021-06-07 19:06:32.0

The technological growth of the last decades has brought many improvements in daily life, but also concerns on how to deal with electronic waste. Electrical and electronic equipment waste is the fastest-growing rate in the industrialized world. One of the elements of electronic equipment is the printed circuit board (PCB) and almost every electronic equipment has a PCB inside it. While waste PCB (WPCB) recycling may result in the recovery of potentially precious materials and the reuse of some components, it is a challenging task because its composition diversity requires a cautious pre-processing stage to achieve optimal recycling outcomes. Our research focused on proposing a method to evaluate the economic feasibility of recycling integrated circuits (ICs) from WPCB. The proposed method can help decide whether to dismantle a separate WPCB before the physical or mechanical recycling process and consists of estimating the IC area from a WPCB, calculating the IC's weight using surface density, and estimating how much metal can be recovered by recycling those ICs. To estimate the IC area in a WPCB, we used a state-of-the-art object detection deep learning model (YOLO) and the PCB DSLR image dataset to detect the WPCB's ICs. Regarding IC detection, the best result was obtained with the partitioned analysis of each image through a sliding window, thus creating new images of smaller dimensions, reaching 86.77% mAP. As a final result, we estimate that the Deep PCB Dataset has a total of 1079.18 g of ICs, from which it would be possible to recover at least 909.94 g of metals and silicon elements from all WPCBs' ICs. Since there is a high variability in the compositions of WPCBs, it is possible to calculate the gross income for each WPCB and use it as a decision criterion for the type of pre-processing.

University of Pernambuco

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