Technical Library | 2015-08-25 13:51:27.0
The stencil printing process is one of the most critical processes in the electronic production. Due to the requirement: "faster and smaller" it is necessary to place components with different paste volume close together without regard to solder paste printing. In our days it is no longer possible to control the solder paste volume only by adjustment of the aperture dimensions. The requirements of solder paste volumes for specific components are realized by different thicknesses of metal sheets in one stencil with so called step stencils. The step-down stencil is required when it is desirable to print fine-pitch devices using a thinner stencil foil, but print other devices using a thicker stencil foil. The paper presents the innovative technology of step-up and step-down stencils in a laser cutting and laser welding process. The step-up/step-down stencil is a special development for the adjustment of solder paste quantity, fulfilling the needs of placement and soldering. This includes the laser cutting and laser welding process as well as the resulting stencil characteristics and the potential of the printing process.
Technical Library | 2019-09-25 04:36:01.0
What is the main function of hot air dry oven? Drying ovens are devices used to remove moisture and other solvents from the items placed inside them through a forced convection process, collecting it elsewhere so that the object becomes dehydrated. A drying oven causes objects to dry out through evaporation. Drying ovens use convection heating,also called air forced, in which the object is heated through air currents. Water from the object escapes into the air, raising the humidity level and causing the semi-solid membranes inside the oven to absorb the water. The end result is that the oven removes water from the object being dried, leaving it dehydrated. Drying ovens contain a system for forcing convection currents to develop, usually either a fan or turbine, which aids in the heating and drying process by ensuring that the hot air circulates,many ovens are equipped with an adjustable ventilation system that allows the user to ensure that the system has an adequate air supply. For details,pls visit our website: https://climatechambers.com/articles&latestnews/what-is-the-main-function-of-hot-air-dry-oven.html
Technical Library | 2020-12-16 18:50:42.0
System operating speeds continue to increase as a function of the consumer demand for such technologies as faster Internet connectivity, video on demand, and mobile communications technology. As a result, new high performance PCB substrates have emerged to address signal integrity issues at higher operating frequencies. These are commonly called low Dk and/or low loss (Df) materials. The published "typical" values found on a product data sheet provide limited information, usually a single construction and resin content, and are derived from a wide range of test methods and test sample configurations. A printed circuit board designer or front end application engineer must be aware that making a design decision based on the limited information found on a product data sheet can lead to errors which can delay a product launch or increase the assembled PCB cost. The purpose of this paper is to highlight critical selection factors that go beyond a typical product data sheet and explain how these factors must be considered when selecting materials for high speed applications
Technical Library | 2021-06-02 19:34:48.0
In recent years, there has been dynamic changes in the industrial environment as a result of further innovations called Industry 4.0 (I.4.0), especially in the field of digital technology and manufacturing. Despite numerous examples of the implementation of Industry 4.0 in enterprises, there is no general framework for the implementation of Industry 4.0 with a detailed schedule. Researching the ways of implementing Industry 4.0 is still a current and unexplored area of research. The main aim of the paper is to present the concept of the theoretical framework for Industry 4.0 implementation based on selected schedules of the Industry 4.0 implementation. The paper was based on information from literature review and analysis of pilot enterprise projects to Industry 4.0 (case study) that were conducted in selected enterprises. The paper presents the key components of the framework of Industry 4.0 and the basic stage of implementing the concept in the enterprises, paying attention to their sequence and time frames. The proposed approach is dedicated to researchers and practitioners who implement the concept of Industry 4.0 in enterprises
Technical Library | 2019-04-07 23:34:10.0
Ingress Protection Test Chamber is used to determine the protection degree of product enclosures,the protection level provided by the enclosure is called IP code,our IP test chamber compeletely follow the standard IEC60529 and others. IP protection grade is an important index of electrical equipment safety protection. Protective-grade systems such as ip, which provide a method of classifying products in terms of dust-proof, waterproof and anti-collision levels of electrical equipment and packaging, which have been recognized by most European countries, as drafted by the International Electrotechnical Association (iec (international electro technical commission). And announced in ied529 (bs en 60529 / 1992) outer packing protection grade (ip code). The level of protection is expressed in terms of IP followed by two numbers, which are used to define the level of protection. The first number indicates the extent of the equipment‘s resistance to dust, or the degree to which people are protected from harm in sealed environments. I represents a level that prevents solid foreign matter from entering, with a maximum level of 6; The second number indicates the extent to which the equipment is waterproof. P represents the level of protection against influent and the highest level is 8. Such as the protection level of the motor ip65. Contact electrical equipment protection and external material protection level (first digit) Electrical equipment waterproof protection level (second digit) . IP is the international code used to identify the protection grade ip grade consists of two numbers, the first number for dust, and the second number for waterproof, the larger the number means the better protection level.
Technical Library | 2020-08-27 01:22:45.0
Initially adopted internal specifications for acceptance of printed circuit boards (PCBs) used for wire bonding was that there were no nodules or scratches allowed on the wirebond pads when inspected under 20X magnification. The nodules and scratches were not defined by measurable dimensions and were considered to be unacceptable if there was any sign of a visual blemish on wire-bondable features. Analysis of the yield at a PCB manufacturer monitored monthly for over two years indicated that the target yield could not be achieved, and the main reasons for yield loss were due to nodules and scratches on the wirebonding pads. The PCB manufacturer attempted to eliminate nodules and scratches. First, a light-scrubbing step was added after electroless copper plating to remove any co-deposited fine particles that acted as a seed for nodules at the time of copper plating. Then, the electrolytic copper plating tank was emptied, fully cleaned, and filtered to eliminate the possibility of co-deposited particles in the electroplating process. Both actions greatly reduced the density of the nodules but did not fully eliminate them. Even though there was only one nodule on any wire-bonding pad, the board was still considered a reject. To reduce scratches on wirebonding pads, the PCB manufacturer utilized foam trays after routing the boards so that they did not make direct contact with other boards. This action significantly reduced the scratches on wire-bonding pads, even though some isolated scratches still appeared from time to time, which caused the boards to be rejected. Even with these significant improvements, the target yield remained unachievable. Another approach was then taken to consider if wire bonding could be successfully performed over nodules and scratches and if there was a dimensional threshold where wire bonding could be successful. A gold ball bonding process called either stand-off-stitch bonding (SSB) or ball-stitch-on-ball bonding (BSOB) was used to determine the effects of nodules and scratches on wire bonds. The dimension of nodules, including height, and the size of scratches, including width, were measured before wire bonding. Wire bonding was then performed directly on various sizes of nodules and scratches on the bonding pad, and the evaluation of wire bonds was conducted using wire pull tests before and after reliability testing. Based on the results of the wire-bonding evaluation, the internal specification for nodules and scratches for wirebondable PCBs was modified to allow nodules and scratches with a certain height and a width limitation compared to initially adopted internal specifications of no nodules and no scratches. Such an approach resulted in improved yield at the PCB manufacturer.
Technical Library | 2019-04-08 23:21:29.0
Climatest Symor® adopts molecular sieve to dry air, the whole system is controlled by microcomputer, when humidity is high, It will start to absorb moisture,when the humidity reach the pre-set value, it will stop absorbing, and then discharge the water to outside the cabinet by heating,again and again by automatic control. The most effective and environment-friendly moisture-absorbing desiccant is molecular sieve, molecular sieve is the microporous crystal material synthesized by silicon and aluminium oxide. In order to keep the crystal net discharge to be zero, atoms with cations are located in the crystal structure.and the cation used in these synthetic crystals is usually sodium. At present, there are two kinds of molecular sieves widely used in the dry box industry: Class A and Class X. Molecular sieves are synthesized, shaped and activated under strictly controlled production processes. The whole controlled sythesis process can ensure consistency of the three-dimensional pore size. 3A molecular sieve pore size is 3 angstroms, 4A molecular sieve pore size is 4 angstroms; 13X molecular sieve pore size is 8.5 angstroms. The working principle of molecular sieve: Molecular sieves adsorb molecules onto the crystal surface by physical attraction force. Since 95% surface area of the molecular sieve is within aperture,it needs to screen the adjacent molecules by different size. Only small size molecules can enter into the inner adsorption surface of the molecular sieve through the crystal aperture. This selective adsorption phenomenon is called molecular sieve effect. The molecular sieve adsorption capacity and charge density (polarity) are further related to the adsorbed molecules. The molecular sieves can further distinguish which of the mixed molecules can be adsorbed and determine to what extent the charge density can allow the molecules to be adsorbed onto the crystal. Water molecules are particularly small (2.6 angstroms), that belong to highly polar molecules (very strong positive and negative electron density), and are easily adsorbed by molecular sieves, even under very low moisture condition,once the water molecules are adsorbed,they will be firmly fixed on the crystal. The environment-friendly moisture absorption device is equipped with molecular sieve. When it’s absorbing, the memory alloy controller is in tensile state, and the spring is in contractive state,which just make the valve contact the outer baffle, this insulates the outside air from inside dry box air to achieve dehumidification purpose; and after molecular sieve absorbed moisture inside dry box and become saturated, the program will automatically control the memory alloy device to shrink it so that the valve reaches the inner baffle position. Meanwhile, due to the shrinkage of the memory alloy, the spring is stretched and the valve is pulled out of the outer baffle,so that the moisture in molecular sieve will be discharged into the outside. after the dehumidifying process finished, the program automatically control and reset the memory alloy and spring,to restart absorbing status.
Technical Library | 2020-07-08 20:05:59.0
There is a compelling need for functional testing of high-speed input/output signals on circuit boards ranging from 1 gigabit per second (Gbps) to several hundred Gbps. While manufacturing tests such as Automatic Optical Inspection (AOI) and In-Circuit Test (ICT) are useful in identifying catastrophic defects, most high-speed signals require more scrutiny for failure modes that arise due to high-speed conditions, such as jitter. Functional ATE is seldom fast enough to measure high-speed signals and interpret results automatically. Additionally, to measure these adverse effects it is necessary to have the tester connections very close to the unit under test (UUT) as lead wires connecting the instruments can distort the signal. The solution we describe here involves the use of a field programmable gate array (FPGA) to implement the test instrument called a synthetic instrument (SI). SIs can be designed using VHDL or Verilog descriptions and "synthesized" into an FPGA. A variety of general-purpose instruments, such as signal generators, voltmeters, waveform analyzers can thus be synthesized, but the FPGA approach need not be limited to instruments with traditional instrument equivalents. Rather, more complex and peculiar test functions that pertain to high-speed I/O applications, such as bit error rate tests, SerDes tests, even USB 3.0 (running at 5 Gbps) protocol tests can be programmed and synthesized within an FPGA. By using specific-purpose test mechanisms for high-speed I/O the test engineer can reduce test development time. The synthetic instruments as well as the tests themselves can find applications in several UUTs. In some cases, the same test can be reused without any alteration. For example, a USB 3.0 bus is ubiquitous, and a test aimed at fault detection and diagnoses can be used as part of the test of any UUT that uses this bus. Additionally, parts of the test set may be reused for testing another high-speed I/O. It is reasonable to utilize some of the test routines used in a USB 3.0 test, in the development of a USB 3.1 (running at 10 Gbps), even if the latter has substantial differences in protocol. Many of the SI developed for one protocol can be reused as is, while other SIs may need to undergo modifications before reuse. The modifications will likely take less time and effort than starting from scratch. This paper illustrates an example of high-speed I/O testing, generalizes failure modes that are likely to occur in high-speed I/O, and offers a strategy for testing them with SIs within FPGAs. This strategy offers several advantages besides reusability, including tester proximity to the UUT, test modularization, standardization approaching an ATE-agnostic test development process, overcoming physical limitations of general-purpose test instruments, and utilization of specific-purpose test instruments. Additionally, test instrument obsolescence can be overcome by upgrading to ever-faster and larger FPGAs without losing any previously developed design effort. With SIs and tests scalable and upward compatible, the test engineer need not start test development for high-speed I/O from scratch, which will substantially reduce time and effort.
