Technical Library | 2016-06-30 14:00:32.0
When designing PLLs in nanometer CMOS, it is essential to validate the closed-loop PLL performance metrics with nanometer SPICE accuracy before going to silicon. Transistor-level, closed-loop PLL verification has been impractical due to traditional SPICE and RF simulator performance and capacity limitations. By using Analog FastSPICE, designers dont have to trade accuracy for performance. Read this white paper to see how AFS: Delivers closed-loop PLL transistor-level verification Supports direct jitter measurements Produces phase noise results correlating within 1-2dB of silicon
Technical Library | 2021-02-04 01:56:56.0
In the present study, a model of closed-loop recycling of copper from PCBs is demonstrated, which involves the sequential application of bioleaching and electrowinning to selectively extract copper. This approach is proposed as part of the solution to resolve the challenging ... doi.org/10.1007/s12649-020-01128-9
Technical Library | 2019-01-10 05:34:07.0
Why do large number of bad blocks generate when SSDs close their lifespan? What's impact on SSDs nomral usage? And how does SSD manage the bad blocks? Just let's take a look at the bad block management in SSDs.
Technical Library | 2022-08-02 17:35:18.0
Saving resources in electronics manufacturing is not an end in itself. It is closely linked with reducing costs and gaining a competitive advantage. However, innovative adhesion and potting technologies in combination with highly functional adhesives and potting media make a significant contribution to the ideal union between economic performance and a reduced ecological footprint.
Technical Library | 2012-04-05 22:53:10.0
In this paper we show how hybrid control and modeling tech-niques can be put to work for solving a problem of industrial relevance in Surface Mount Technology (SMT) manufacturing. In particular, by closing the loop over the stencil printing process, we ob
Technical Library | 2017-11-03 13:34:15.0
As with any production industry, businesses in the PCB industry need to maintain a healthy balance between the components they keep in stock and those they use for meet client orders. Ordering too many components comes with serious disadvantages, as does not ordering enough, and PCB manufacturers need to stay as close as possible to a happy medium between the two.
Technical Library | 1999-05-06 14:46:09.0
Semiconductor manufacturing is characterized by very complex process flows made up of individual process steps, many of which are built to very close tolerances. Furthermore, there are complex interactions in these process flows, whereby each process step can affect many other steps, and each final device parameter might be determined by the results from many inputs...
Technical Library | 1999-05-07 10:23:43.0
Software decoding of Dolby Digital allows it to become a baseline capability on the PC, with greater flexibility than a hardware approach. Intel's MMX™ technology provides instructions that can significantly speed up the execution of the Dolby Digital decoder, freeing up the processor to perform other tasks such as video decoding and/or audio enhancement. Intel has worked closely with Dolby Laboratories to define an implementation of Dolby Digital based on MMX technology that has achieved Dolby's certification of quality.
Technical Library | 1999-08-09 11:09:42.0
Organic Solderability Preservatives (OSPs), also known as anti-tarnish, on bare copper printed circuit boards (PCBs) are becoming more prevalent in the electronics industry as the low-cost replacement to Hot Air Solder Leveling (HASL). Introducing the anti-tarnish alternative into the customer sites requires working closely with the coating supplier, assembler, and Original Equipment Manufacturer (OEM) to gain a mutual understanding of respective processing concerns and finished product requirements.
Technical Library | 2001-04-24 10:47:02.0
Board-level circuits today routinely run at speeds of 100 MHz or more and are composed of dozens of complex interacting VLSI components. To design such circuits in a timely and correct manner it is necessary to pay close attention to circuit timing early in the design cycle. At fast clock speeds, managing component and interconnect propagation delay becomes a key aspect of circuit design. It is imperative that the critical paths on a circuit and the slack available for interconnect delay consumption be identified early, and drive subsequent stages in the design flow.
