Technical Library | 1999-07-21 08:49:49.0
As the role of direct-chip-attachment increases in the electronics industry, the reliability and performance of COB packaging materials becomes an increasing concern. Although many factors influence component reliability, the biggest determinants of performance are often the glass transition temperature (Tg) and the coefficient of thermal expansion (CTE) of the encapsulant or underfill. This paper discusses exactly what these properties are, how they are measured, and why they are important to device-reliability.
Technical Library | 2008-02-04 12:13:38.0
Engineers are always striving to make a lighter, faster and stronger PCB. In order to achieve their designs, engineers must turn to alternative materials to enhance their designs. There are many materials that allow for thermal, coefficient of thermal expansion (CTE) and rigidity. Many times if a material enables an engineer to have CTE they will have to sacrifice thermal. Currently carbon composite laminates are being used in order to achieve an ideal PCB with thermal, CTE and rigidity with almost no weight premiums.
Technical Library | 2008-11-13 00:06:32.0
The electronics industry is facing issues with hot spots, solder joint stresses and Coefficient of Thermal Expansion (CTE) mismatch between PCB and IC substrate. Flip chip type packages for example have very low CTE compared to traditional PCB material. Thus it is necessary to have low CTE printed circuit boards in order to keep solder joint intact with such low CTE packages. There are currently several materials available in the market to address thermal and CTE challenges but each material has its own advantages and limitations...
Technical Library | 2014-06-26 16:43:12.0
Edgebond adhesives have been widely used by the industry for improving the shock performance of area array packages. Most of the studies focus on the impact of material properties, such as coefficient of thermal expansion (CTE) and glass transition temperature (Tg), on reliability at room temperature. However, the operating temperature of a component on the printed circuit board bonded with edgebond adhesive can be close to or exceed Tg of the adhesive, where the material properties may be very different than at room temperature.
Technical Library | 2021-08-11 01:00:37.0
Conformal coatings and potting materials continue to create issues for the electronics industry. This webinar will dig deeper into the failure modes of these materials, specifically issues with Coefficient of Thermal Expansion (CTE), delamination, cracking, de-wetting, pinholes/bubbles and orange peel issues with conformal coatings and what mitigation techniques are available. Similarly, this webinar will look at the failure modes of potting materials, (e.g Glass Transition Temperature (Tg), PCB warpage, the effects of improper curing and potential methods for correcting these situations.
Technical Library | 2018-11-07 20:48:01.0
Glass offers a number of advantages as a dielectric material, such as a low coefficient of thermal expansion (CTE), high dimensional stability, high thermal conductivity and suitable dielectric constant. These properties make glass an ideal candidate for, among other things, package substrate and high-frequency PCB applications. We report here a novel process for the production of printed circuit boards and integrated circuit packaging using glass as both a dielectric medium and a platform for wiring simultaneously.
Technical Library | 2021-01-13 21:34:29.0
Package-on-Package (PoP) is a popular technology for fabricating chipsets of accelerated processing units. However, the coefficient of thermal expansion mismatch between Si chips and polymer substrates induces thermal warpage during the reflow process. As such, the reflow temperature and reliability of solder joints are critical aspects of PoP. Although Sne58Bi is a good candidate for low-temperature processes, its brittleness causes other reliability issues. In this study, an in-situ observation was performed on composite solders (CSs) made of ...
Technical Library | 2020-12-16 18:38:49.0
Fabrication of large structures using out-of-autoclave prepreg materials will lead to a great amount of savings in manufacturing costs. In the out-of-autoclave processing method, the presence of voids inside the laminate has been an issue due to the lack of high pressure during manufacturing. This study aims primarily to observe the moisture absorption response of composite samples containing different levels of void. By changing the vacuum level inside the bag during the manufacturing process, three different unidirectional laminates at three levels of void have been manufactured. After immersing the samples in warm water at 60°C for about one year, the moisture absorption level was monitored and then diffusion coefficients were calculated using Fick's law. Results show that the moisture absorption coefficient changes by %8 within the experimental range of void contents. The mechanical behaviour of these laminates has been studied at four different moisture levels by performing dynamic mechanical analysis (DMA) and short beam shear tests. Empirical results indicate that, in general, interlaminar shear strength and glass transition temperature decrease by moisture build-up inside the samples. DiBenedetto equation is proposed to make a correlation between the moisture content and glass transition temperature.
Technical Library | 2020-01-01 17:06:52.0
The majority of electronic failures occur due to thermally induced stresses and strains caused by excessive differences in coefficients of thermal expansion (CTE) across materials.CTE mismatches occur in both 1st and 2nd level interconnects in electronics assemblies. 1st level interconnects connect the die to a substrate. This substrate can be underfilled so there are both global and local CTE mismatches to consider. 2nd level interconnects connect the substrate, or package, to the printed circuit board (PCB). This would be considered a "board level" CTE mismatch. Several stress and strain mitigation techniques exist including the use of conformal coating.
Technical Library | 2011-10-20 22:03:30.0
Results of FEM modelling of thermal stress analysis in printed circuit boards are given in the article. It is shown that thermal stress alone is not solely caused by differences in coefficients of thermal expansion of individual layers. The emergence of thermal stress is subject to both the layered structure of the wall and given boundary conditions, as well as the existence of a temperature gradient in the direction normal to the surface of the wall. A practical application focuses on the issue of recycling of PCB with the effort to achieve separation of layers due to thermal stress. Role modelling of thermal stress in this area lies in predicting the possibility of separation, depending on the type of thermal stress and material parameters.
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