Technical Library | 2021-01-28 01:55:00.0
Printed circuit board surface finishes are a topic of constant discussion as environmental influences, such as the Restriction of Hazardous Substances (RoHS) Directive or technology challenges, such as flip chip and 01005 passive components, initiate technology changes. These factors drive the need for greater control of processing characteristics like coplanarity and solderability, which influence the selection of surface finishes and impact costs as well as process robustness and integrity. The ideal printed circuit board finish would have good solderability, long shelf life, ease of fabrication/processing, robust environmental performance and provide dual soldering/wirebonding capabilities; unfortunately no single industry surface finish possesses all of these traits. The selection of a printed circuit board surface finish is ultimately a series of compromises for a given application.
Technical Library | 2017-11-15 22:49:14.0
While a significant level of voiding can be tolerated in solder joints where electrical conductivity is the main requirement, voiding at any level severely compromises thermal conductivity. For example, in LED lighting modules effective conduction of heat through the 1st level die attach to the substrate and then through the 2nd level attach to the heat sink is critical to performance so that voiding in the solder joints at both levels must be minimized. (...) In this paper, the authors will review the factors that influence the incidence of voids in small and large area solder joints that simulate, respectively, the 1st and 2nd level joints in LED modules and discuss mitigation strategies appropriate to each level. They will also report the results of a study on the effect on the incidence of voids of flux medium formulation and the optimization of the thermal profile to ensure that most of the volatiles are released early in the reflow process.
Technical Library | 2019-04-10 22:08:31.0
The stimulating impact of the automotive industry has sharpened focus on immersion tin (i-Sn) more than ever before. Immersion tin with its associated attributes, is well placed to fulfill the requirements of such a demanding application. In an environment dominated by reliability, the automotive market not only has very stringent specifications but also demands thorough qualification protocols. Qualification is ultimately a costly exercise. The good news is that i-Sn is already qualified by many tier one OSATs. The focus of this paper is to generate awareness of the key factors attributed to soldering i-Sn. Immersion tin is not suitable for wire bonding but ultimately suited for multiple soldering applications. The dominant topics of this paper will be IMC formations in relation to reflow cycles and the associated solderability performance. Under contamination free conditions, i-Sn can provide a solderable finish even after multiple reflow cycles. The reflow conditions employed in this paper are typical for lead free soldering environments and the i-Sn thicknesses are approximately 1 μm.
Technical Library | 2023-03-16 18:51:43.0
Conductive anodic filament (CAF) formation was first reported in 1976.1 This electrochemical failure mode of electronic substrates involves the growth of a copper containing filament subsurface along the epoxy-glass interface, from anode to cathode. Despite the projected lifetime reduction due to CAF, field failures were not identified in the 1980s. Recently, however, field failures of critical equipment have been reported.2 A thorough understanding of the nature of CAF is needed in order to prevent this catastrophic failure from affecting electronic assemblies in the future. Such an understanding requires a comprehensive evaluation of the factors that enhance CAF formation. These factors can be grouped into two types: (1) internal variables and (2) external influences. Internal variables include the composition of the circuit board material, and the conductor metallization and configuration (i.e. via to via, via to surface conductor or surface conductors to surface conductors). External influences can be due to (1) production and (2) storage and use. During production, the flux or hot air solder leveling (HASL) fluid choice, number and severity of temperature cycles, and the method of cleaning may influence CAF resistance. During storage and use, the principal concern is moisture uptake resulting from the ambient humidity. This paper will report on the relationship between these various factors and the formation of CAF. Specifically, we will explore the influences of printed wiring board (PWB) substrate choice as well as the influence of the soldering flux and HASL fluid choices. Due to the ever-increasing circuit density of electronic assemblies, CAF field failures are expected to increase unless careful attention is focused on material and processing choices.
Technical Library | 2018-07-18 16:28:26.0
Reduction of first pass defects in the SMT assembly process minimizes cost, assembly time and improves reliability. These three areas, cost, delivery and reliability determine manufacturing yields and are key in maintaining a successful and profitable assembly process. It is commonly accepted that the solder paste printing process causes the highest percentage of yield challenges in the SMT assembly process. As form factor continues to get smaller, the challenge to obtain 100% yield becomes more difficult.This paper will identify defects affecting SMT yields in the printing process and discuss their Root Cause. Outer layer copper weight and surface treatment will also be addressed as to their effect on printability. Experiments using leadless and emerging components will be studied and root cause analysis will be presented
Technical Library | 2023-01-10 20:15:42.0
Over the past years there has been consistent growth in the use of electroless nickel / immersion gold (ENIG) as a final finish. The finish is now frequently being used for PBGA, CSP, QFP and COB and more recently gathered considerable interest as a low cost under-bump metallization for flip chip bumping application. One of the largest users for this finish has been the telecommunication industry, were millions of square meters of PCBs with ENIG have been successfully used. The nickel layer offers advantages such as multiple soldering cycles and hand reworks without copper dissolution being a factor. The nickel also acts as a reinforcement to improve through-hole and blind micro via thermal integrity. In addition the nickel layer offers advantages such as co-planarity, Al-wire bondability and the use as contact surface for keypads or contact switching. Especially those pads, which are not covered by solder need a protective coating in corrosive environment – such as high humidity or pollutant gas.
Technical Library | 2020-08-05 18:49:32.0
The evolution of internet-enabled mobile devices has driven innovation in the manufacturing and design of technology capable of high-frequency electronic signal transfer. Among the primary factors affecting the integrity of high-frequency signals is the surface finish applied on PCB copper pads – a need commonly met through the electroless nickel immersion gold process, ENIG. However, there are well-documented limitations of ENIG due to the presence of nickel, the properties of which result in an overall reduced performance in high-frequency data transfer rate for ENIG-applied electronics, compared to bare copper. An innovation over traditional ENIG is a nickel-less approach involving a special nano-engineered barrier designed to coat copper contacts, finished with an outermost gold layer. In this paper, assemblies involving this nickel-less novel surface finish have been subjected to extended thermal exposure, then intermetallics analyses, contact/sheet resistance comparison after every reflow cycle (up to 6 reflow cycles) to assess the prevention of copper atoms diffusion into gold layer, solder ball pull and shear tests to evaluate the aging and long-term reliability of solder joints, and insertion loss testing to gauge whether this surface finish can be used for high-frequency, high density interconnect (HDI) applications.
Technical Library | 2023-08-04 15:38:36.0
The MicroLeadFrame® (MLF®)/Quad Flat No-Lead (QFN) packaging solution is extremely popular in the semiconductor industry. It is used in applications ranging from consumer electronics and communications to those requiring high reliability performance, such as the automotive industry. The wide acceptance of this packaging design is primarily due to its flexible form factors, size, scalability and thermal dissipation capabilities. The adaptation and acceptance of MLF/QFN packages in automotive high reliability applications has led to the development of materials and processes that have extended its capabilities to meet the performance and quality requirements. One of process developments that is enabling the success of the MLF/QFN within the automotive industry has been the innovation of side wettable flanks that provide the capability to inspect the package lead to printed circuit board (PCB) interfaces for reliable solder joints. Traditionally, through-board X-ray was the accepted method for detecting reliable solder joints for leadless packages. However, as PBC layer counts and routing complexities have increased, this method to detect well-formed solder fillets has proven ineffective and incapable of meeting the inspection requirements. To support increased reliability and more accurate inspection of the leadless package solder joints, processes to form side-wettable flanks have been developed. These processes enable the formation of solder fillets that are detectable using state-of-the-art automated optical inspection (AOI) equipment, providing increased throughput for the surface mount technology (SMT) processes and improved quality as well.
