Technical Library | 2024-08-29 18:30:46.0
The mechanical experience of consumption (i.e., feel, softness, and texture) of many foods is intrinsic to their enjoyable consumption, one example being the habit of twisting a sandwich cookie to reveal the cream. Scientifically, sandwich cookies present a paradigmatic model of parallel plate rheometry in which a fluid sample, the cream, is held between two parallel plates, the wafers. When the wafers are counterrotated, the cream deforms, flows, and ultimately fractures, leading to separation of the cookie into two pieces. We introduce Oreology (/Oriːˈɒl@dʒi/), from the Nabisco Oreo for "cookie" and the Greek rheo logia for "flow study," as the study of the flow and fracture of sandwich cookies. Using a laboratory rheometer, we measure failure mechanics of the eponymous Oreo's "creme" and probe the influence of rotation rate, amount of creme, and flavor on the stress–strain curve and postmortem creme distribution. The results typically show adhesive failure, in which nearly all (95%) creme remains on one wafer after failure, and we ascribe this to the production process, as we confirm that the creme-heavy side is uniformly oriented within most of the boxes of Oreos. However, cookies in boxes stored under potentially adverse conditions (higher temperature and humidity) show cohesive failure resulting in the creme dividing between wafer halves after failure. Failure mechanics further classify the creme texture as "mushy." Finally, we introduce and validate the design of an open-source, three-dimensionally printed Oreometer powered by rubber bands and coins for encouraging higher precision home studies to contribute new discoveries to this incipient field of study
Technical Library | 2014-06-12 16:40:19.0
Occurrence of popcorn in IC packages while assembling them onto the PCB is a well known moisture sensitive reliability issues, especially for surface mount packages. Commonly reflow soldering simulation process is conducted to assess the impact of assembling IC package onto PCB. A strain gauge-based instrumentation is developed to investigate the popcorn effect in surface mount packages during reflow soldering process. The instrument is capable of providing real-time quantitative information of the occurrence popcorn phenomenon in IC packages. It is found that the popcorn occur temperatures between 218 to 241°C depending on moisture soak condition, but not at the peak temperature of the reflow process. The presence of popcorn and delamination are further confirmed by scanning acoustic tomography as a failure analysis.
WASET - World Academy of Science, Engineering and Technology
Technical Library | 2021-01-21 02:04:27.0
Traditional single level microvia structures are generally considered the most robust type of interconnection within a printed wire board (PWB) substrate. The rapid implementation of HDI technology now commonly requires between 2, 3 or 4 levels of microvias sequentially processed into the product. Recent OEM funded reliability testing has confirmed that by increasing the levels (stack height) these structures are proving less reliable, when compared to their single or double level counterparts. Recently false positive results have been recorded on products tested with traditional thermal shock testing methodology (cycling between -40°C and 125°C, or 145°C). A number of companies are incurring product failures resulting in increased costs associated with replacing the circuit boards, components and added labour.
Technical Library | 2014-07-02 16:46:09.0
Growth behaviors of intermetallic compounds (IMCs) and Kirkendall voids in Cu/Sn/Cu microbump were systematically investigated by an in-situ scanning electron microscope observation. Cu–Sn IMC total thickness increased linearly with the square root of the annealing time for 600 h at 150°C, which could be separated as first and second IMC growth steps. Our results showed that the growth behavior of the first void matched the growth behavior of second Cu6Sn5, and that the growth behavior of the second void matched that of the second Cu3Sn. It could be confirmed that double-layer Kirkendall voids growth kinetics were closely related to the Cu–Sn IMC growth mechanism in the Cu/Sn/Cu microbump, which could seriously deteriorate the mechanical and electrical reliabilities of the fine-pitch microbump systems
Technical Library | 2015-07-01 16:51:43.0
Aerospace and military companies continue to exercise RoHS exemptions and to intensively research the long term attachment reliability of RoHS compliant solders. Their products require higher vibration, drop/shock performance, and combined-environment reliability than the conventional SAC305 alloy provides. The NASA-DoD Lead-Free Electronics Project confirmed that pad cratering is one of the dominant failure modes that occur in various board level reliability tests, especially under dynamic loading. One possible route to improvement of the mechanical and thermo-mechanical properties of solder joints is the use of Pb-free solders with lower process temperatures. Lower temperatures help reduce the possibility of damaging the boards and components, and also may allow for the use of lower Tg board materials which are less prone to pad cratering defects. There are several Sn-Ag-Bi and Sn-Ag-Cu-Bi alloys which melt about 10°C lower than SAC305. The bismuth in these solder compositions not only reduces the melting temperature, but also improves thermo-mechanical behavior. An additional benefit of using Bi-containing solder alloys is the possibility to reduce the propensity to whisker growth
Technical Library | 2020-07-22 19:39:05.0
The PWB industry needs to complete reliability testing in order to define the minimum copper wrap plating thickness requirement for confirming the reliability of PTH structures. Predicting reliability must ensure that the failure mechanism is demonstrated as a wear-out failure mode because a plating wrap failure is unpredictable. The purpose of this study was to quantify the effects of various copper wrap plating thicknesses through IST testing followed by micro sectioning to determine the failure mechanism and identify the minimum copper wrap thickness required for a reliable PWB. Minimum copper wrap plating thickness has become an even a bigger concern since designers started designing HDI products with buried vias, microvias and through filled vias all in one design. PWBs go through multiple plating cycles requiring planarization after each plating cycle to keep the surface copper to a manageable thickness for etching. The companies started a project to study the relationship between Copper wrap plating thickness and via reliability. The project had two phases. This paper will present findings from both Phase 1 and Phase 2.
Technical Library | 2022-12-05 16:28:06.0
The work evaluates the impact of latent heat (LH) absorbed or released by a solder alloy during melting or solidification, respectively, on changes of dimensions of materials surrounding of the solder alloy. Our sample comprises a small printed circuit board (PCB) with a blind via filled with lead-free alloy SAC305. Differential scanning calorimetry (DSC) was employed to obtain the amount of LH per mass and a thermomechanical analyzer was used to measure the thermally induced deformation. A plateau during melting and a peak during solidification were detected during the course of dimension change. The peak height reached 1.6 μm in the place of the heat source and 0.3 μm in the distance of 3 mm from the source. The data measured during solidification was compared to a numerical model based on the finite element method. An excellent quantitative agreement was observed which confirms that the transient expansion of PCB during cooling can be explained by the release of LH from the solder alloy during solidification. Our results have important implications for the design of PCB assemblies where the contribution of recalescence to thermal stress can lead to solder joint failure.
Technical Library | 2021-07-27 14:54:26.0
Fast forward to current time. Today, our society embraces cleanliness. We expect, demand, and evaluate cleanliness in almost every aspect of our lives. We wash our cars and pets. We maintain high cleanliness standards in our hotels and public spaces. We require cleanliness in our restaurants and hospitals. We sanitize our hands throughout the day to prevent illness. We live in a clean-centric culture. While we drive clean cars, stay in clean hotels and eat clean food, there is one part of our life where we actually abandoned cleanliness. Many of the circuit assemblies that affect almost every aspect of our daily lives are no longer required to be clean. Even though our life experience confirms the link between cleanliness and reliability, happiness, health, and safety, circuit assemblies no longer maintain that "cleanliness is next to Godliness" status. This was not always the case. There was a time when virtually all circuit assemblies were cleaned. The removal of flux and other process-related contamination was commonplace. Cleaning was as normal as soldering. As we bring history into current time, one may relate the fall of Rome and its adoption of personal hygiene and the subsequent decline in human health to the large-scale abandonment of cleanliness expectations of circuit assemblies and the subsequent reliability issues it has created. How did this happen? Has history repeated itself?
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