Technical Library | 2008-11-20 00:46:10.0
The Sn/Ag/Cu family of alloys is the leading candidate for a lead-free alternative. The first part of this study was to determine if there is any significant difference between Sn/Ag/Cu alloys when used in automatic soldering equipment in terms of copper build-up in the system. The study compared two Sn/Ag/Cu alloys to determine if at processing temperatures one alloy would absorb less copper than the other alloy.
Technical Library | 2020-09-02 22:14:36.0
The demand for miniaturization and higher density electronic products has continued steadily for years, and this trend is expected to continue, according to various semiconductor technology and applications roadmaps. The printed circuit board (PCB) must support this trend as the central interconnection of the system. There are several options for fine line circuitry. A typical fine line circuit PCB product using copper foil technology, such as the modified semi-additive process (mSAP), uses a thin base copper layer made by pre-etching. The ultrathin copper foil process (SAP with ultrathin copper foil) is facing a technology limit for the miniaturization due to copper roughness and thickness control. The SAP process using sputtered copper is a solution, but the sputtering process is expensive and has issues with via plating. SAP using electroless copper deposition is another solution, but the process involved is challenged to achieve adequate adhesion and insulation between fine-pitch circuitries. A novel catalyst system--liquid metal ink (LMI)--has been developed that avoids these concerns and promotes a very controlled copper thickness over the substrate, targeting next generation high density interconnect (HDI) to wafer-level packaging substrates and enabling 5-micron level feature sizes. This novel catalyst has a unique feature, high density, and atomic-level deposition. Whereas conventional tin-palladium catalyst systems provide sporadic coverage over the substrate surface, the deposited catalyst covers the entire substrate surface. As a result, the catalyst enables improved uniformity of the copper deposition starting from the initial stage while providing higher adhesion and higher insulation resistance compared to the traditional catalysts used in SAP processes. This article discusses this new catalyst process, which both proposes a typical SAP process using the new catalyst and demonstrates the reliability improvements through a comparison between a new SAP PCB process and a conventional SAP PCB process.
Technical Library | 2013-04-25 11:42:01.0
Specification and control of surface roughness of copper conductors within printed circuit boards (PCBs) are increasingly desirable in multi-GHz designs as a part of signal-integrity failure analysis on high-speed PCBs. The development of a quality-assurance method to verify the use of foils with specified roughness grade during the PCB manufacturing process is also important... First published in the 2012 IPC APEX EXPO technical conference proceedings.
Technical Library | 2009-02-13 12:29:39.0
To meet the market demand for a best-in-class, low-cost leadfree alloy for wave, selective and dip soldering
Technical Library | 2015-11-12 19:04:51.0
In order to provide the functionality in today’s electronics, printed circuit boards are approaching the complexity of semiconductors. For flexible circuits with 1 mil lines and spaces, this means no nodules, no pits, and excellent ductility with thinner deposits. One of the areas that has to change to get to this plateau of technology is acid copper plating. Acid copper systems have changed in minor increments since their introduction decades ago. However, the basic cell design using soluble anodes in slabs or baskets has for the most part remained the same. Soluble, phosphorized, copper anodes introduce particulate and limits the ability to control plating distribution.
Technical Library | 2015-12-23 16:57:27.0
The onset of copper barrel cracks is typically induced by the presence of manufacturing defects. In the absence of discernible manufacturing defects, the causes of copper barrel cracks in printed circuit board (PCB) plated through holes is not well understood. Accordingly, there is a need to determine what affects the onset of barrel cracks and then control those causes to mitigate their initiation.The objective of this research is to conduct a design of experiment (DOE) to determine if there is a relationship between PCB fabrication processes and the prevalence of fine barrel cracks. The test vehicle used will be a 16-layer epoxy-based PCB that has two different sized plated through holes as well as buried vias.
Technical Library | 2014-07-24 16:26:34.0
Wire bonding a die to a package has traditionally been performed using either aluminum or gold wire. Gold wire provides the ability to use a ball and stitch process. This technique provides more control over loop height and bond placement. The drawback has been the increasing cost of the gold wire. Lower cost Al wire has been used for wedge-wedge bonds but these are not as versatile for complex package assembly. The use of copper wire for ball-stitch bonding has been proposed and recently implemented in high volume to solve the cost issues with gold. As one would expect, bonding with copper is not as forgiving as with gold mainly due to oxide growth and hardness differences. This paper will examine the common failure mechanisms that one might experience when implementing this new technology.
Technical Library | 2016-09-08 16:27:49.0
In this investigation a test matrix was completed utilizing 900 electrodes (small circuit board with parallel copper traces on FR-4 with LPI soldermask at 6, 10 and 50 mil spacing): 12 ionic contaminants were applied in five concentrations to three different spaced electrodes with five replicas each (three different bare copper trace spacing / five replications of each with five levels of ionic concentration). The investigation was to assess the electrical response under controlled heat and humidity conditions of the known applied contamination to electrodes, using the IPC SIR (surface insulation resistance) J-STD 001 limits and determine at what level of contamination and spacing the ionic / organic residue has a failing effect on SIR.
Technical Library | 2024-06-23 21:57:16.0
Two extremes of reflow time scale for copper pillar flip chip solder joints were explored in this study. Sn-2.5Ag solder capped pillars were joined to laminate substrates using either conventional forced convection reflow or the controlled impingement of a defocused infrared laser. The laser reflow joining process was accomplished with an order of magnitude reduction in time above liquidus and a similar increase in solidification cooling rate. The brief reflow time and rapid cooling of a laser impingement reflow necessarily affects all time and temperature dependent phenomena characteristic of reflowed molten solder. These include second phase precipitate dissolution, base metal (copper) dissolution, and the extent of surface wetting. This study examines the reflow dependent microstructural aspects of flip chip Sn-Ag joints on samples of two different size scales, the first with copper pillars of 70μm diameter on 120μm pitch and the second with 23μm diameter pillars on a 40μm pitch. The length scale of Pb-free solder joints is known to affect the Sn grain solidification structure; Sn grain morphology will be noted across both reflow time and joint length scales. Sn grain morphology was further found to be dependent on the extent of surface wetting when such wetting circumvented the copper diffusion barrier layer. Microstructural analysis also will include a comparison of intermetallic structures formed; including the size and number density of second phase Ag3Sn precipitates in the joint and the morphology and thickness of the interfacial intermetallics formed on the pillar and substrate surfaces.
Technical Library | 2018-05-23 12:12:43.0
Driven by miniaturization, cost reduction and tighter requirements for electrical and thermal performance, the use of lead-frame based bottom-termination components (LF-BTC) as small-outline no-leads (SON), quad-flat no leads (QFN) packages etc., is increasing. However, a major distractor for the use of such packages in high-reliability applications has been the lack of a visible solder (toe) fillet on the edge surface of the pins: because the post-package assembly singulation process typically leaves bare copper leadframe at the singulation edge, which is not protected against oxidation and thus does not easily solder-wet, a solder fillet (toe fillet) does not generally develop.
