Technical Library | 2023-02-13 19:23:18.0
Spontaneously forming tin whiskers, which emerge unpredictably from pure tin surfaces, have regained prevalence as a topic within the electronics research community. This has resulted from the ROHS-driven conversion to "lead-free" solderable finish processes. Intrinsic stresses (and/or gradients) in plated films are considered to be a primary driving force behind the growth of tin whiskers. This paper compares the formation of tin whiskers on nanocrystalline and conventional polycrystalline copper deposits. Nanocrystalline copper under-metal deposits were investigated, in terms of their ability to mitigate whisker formation, because of their fine grain size and reduced film stress. Pure tin films were deposited using matte and bright electroplating, electroless plating, and electron beam evaporation. The samples were then subjected to thermal cycling conditions in order to expedite whisker growth. The resultant surface morphologies and whisker formations were evaluated.
Technical Library | 2023-08-04 15:27:30.0
A designed experiment evaluated the influence of several variables on appearance and strength of Pb-free solder joints. Components, with leads finished with nickel-palladium-gold (NiPdAu), were used from Texas Instruments (TI) and two other integrated circuit suppliers. Pb-free solder paste used was tin-silver-copper (SnAgCu) alloy. Variables were printed wiring board (PWB) pad size/stencil aperture (the pad finish was consistent; electrolysis Ni/immersion Au), reflow atmosphere, reflow temperature, Pd thickness in the NiPdAu finish, and thermal aging. Height of solder wetting to component lead sides was measured for both ceramic plate and PWB soldering. A third response was solder joint strength; a "lead pull" test determined the maximum force needed to pull the component lead from the PWB. This paper presents a statistical analysis of the designed experiment. Reflow atmosphere and pad size/stencil aperture have the greatest contribution to the height of lead side wetting. Reflow temperature, palladium thickness, and preconditioning had very little impact on side-wetting height. For lead pull, variance in the data was relatively small and the factors tested had little impact.
Technical Library | 2024-04-08 15:46:36.0
A designed experiment evaluated the influence of several variables on appearance and strength of Pb-free solder joints. Components, with leads finished with nickel-palladium-gold (NiPdAu), were used from Texas Instruments (TI) and two other integrated circuit suppliers. Pb-free solder paste used was tin-silver-copper (SnAgCu) alloy. Variables were printed wiring board (PWB) pad size/stencil aperture (the pad finish was consistent; electrolysis Ni/immersion Au), reflow atmosphere, reflow temperature, Pd thickness in the NiPdAu finish, and thermal aging. Height of solder wetting to component lead sides was measured for both ceramic plate and PWB soldering. A third response was solder joint strength; a "lead pull" test determined the maximum force needed to pull the component lead from the PWB. This paper presents a statistical analysis of the designed experiment. Reflow atmosphere and pad size/stencil aperture have the greatest contribution to the height of lead side wetting. Reflow temperature, palladium thickness, and preconditioning had very little impact on side-wetting height. For lead pull, variance in the data was relatively small and the factors tested had little impact.
Technical Library | 2021-11-03 16:49:59.0
Ultrathin bare die chips were soldered using a novel soldering technology. Using homogeneous flash light generated by high-power xenon flash lamp the dummy components and the bare die NFC chips were successfully soldered to copper tracks on polyimide (PI) and polyethylene terephthalate (PET) flex foils by using industry standard Sn-Ag-Cu lead free alloys. Due to the selectivity of light absorption, a limited temperature increase was observed in the PET substrates while the chip and copper tracks were rapidly heated to a temperatures above the solder melting temperature. This allowed to successfully soldered components onto the delicate polyethylene foil substrates using lead-free alloys with liquidus temperatures above 200 °C. It was shown that by preheating components above the decomposition temperature of solder paste flux with a set of short low intensity pulses the processing window could be significantly extended compared to the process with direct illumination of chips with high intensity flash pulse. Furthermore, it was demonstrated that with localized tuning of pulse intensity components having different heat capacity could be simultaneously soldered using a single flash pulse.
Technical Library | 2010-07-08 19:49:59.0
Aging characteristics of new lead free solder alloys are in question by many experts because of higher amount of tin’s effect on the diffusion of other metals, primarily copper, to create undesirable boundary intermetallics over long periods of time and even moderately elevated temperatures. A primary layer of intermetallics, Cu6Sn5 forms as the liquid solder makes contact with the solid copper substrate. This reaction however ceases as the solder temperature falls below that of liquidus. A secondary intermetallic Cu3Sn1, an undesirable weak and brittle layer, is thought to form over time and may be accelerated by even mildly elevated temperatures in electronic modules such as laptops under power. This project was designed to quantify the growth rate of Cu3Sn1 over an extended period of time in a thermal environment similar to a laptop in the power on mode.
Technical Library | 2018-05-17 11:14:52.0
Intermetallic compound (IMC) growth is being studied in earnest in this past decade because of its significant effect the solder joint reliability. It appears that from numerous investigations conducted, excessive growth of IMC could lead to solder joint failure. Leading to this, many attempts has been made to determine the actual IMC thickness. However, precise and true representation of the growth in the actual 3D phenomenon from 2D cross-section investigations has remained unclear. This paper will focus on the measuring the IMC thickness using 3D surface profilometer (Alicona Focus G4). Lead free solder, Sn3.0Ag0.5Cu (SAC305) was soldered onto copper printed circuit board (Cu PCB). The samples were then subjected to thermal cycle (TC) storage process with temperature range from 0 °C to 100 °C for 200 cycles and up to 1000 cycles were completed.
Technical Library | 2019-02-13 13:45:11.0
Development of information and telecommunications network is outstanding in recent years, and it is required for the related equipment such as communication base stations, servers and routers, to process huge amount of data in no time. As an electrical signal becomes faster and faster, how to prevent signal delay by transmission loss is a big issue for Printed Circuit Boards (PCB) loaded on such equipments. There are two main factors as the cause of transmission loss; dielectric loss and conductor loss. To decrease the dielectric loss, materials having low dielectric constant and low loss tangent have been developed. On the other hand, reducing the surface roughness of the copper foil itself to be used or minimizing the surface roughness by modifying surface treatment process of the conductor patterns before lamination is considered to be effective in order to decrease the conductor loss. However, there is a possibility that reduction in the surface roughness of the conductor patterns will lead to the decrease in adhesion of conductor patterns to dielectric resin and result in the deterioration of reliability of PCB itself. In this paper, we will show the evaluation results of adhesion performance and electrical properties using certain type of dielectric material for high frequency PCB, several types of copper foil and several surface treatment processes of the conductor patterns. Moreover, we will indicate a technique from the aspect of surface treatment process in order to ensure reliability and, at the same time, to prevent signal delay at the signal frequency over 20 GHz.
Technical Library | 2018-01-17 22:47:02.0
Fine pitch copper (Cu) Pillar bump has been growing adoption in high performance and low-cost flip chip packages. Higher input/output (I/O) density and very fine pitch requirements are driving very small feature sizes such as small bump on a narrow pad or bond-on-lead (BOL) interconnection, while higher performance requirements are driving increased current densities, thus assembling such packages using a standard mass reflow (MR) process and maintaining its performance is a real and serious challenge. (...) In this study a comprehensive finding on the assembly challenges, package design, and reliability data will be published. Originally published in the SMTA International 2016
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