Technical Library | 2019-05-29 01:47:22.0
1.Vias near SMD pads: Solder can flow into the via after melted. As a result cold joint will appear in the end. Check the picture below. 2.Vias on SMD pads: Solder can flow into the via more easier after melted. Check the picture below. 3.Via opening without soldermask covered. When workers solder TH parts by hand, soldering iron can touch vias sometime, then tiny amounts molten solder will stay on vias. This can lead to electrical short easily. We recommend you make all vias tenting (covered by solder mask) if it is possible.
PCBNPI-Professional PCB Fab/PCB Assembly Service Provider From China
Technical Library | 1999-05-07 08:45:39.0
Fine pitch SMT devices, although certainly not new, present more of an assembly processing challenge than 50 mil pitch devices. In fact it seems that the finer the pitch the more difficult or narrower the process window becomes. Besides the pitch of the leads being less on fine pitch devices narrower pad width on the board is typical. With fine pitch designs the board fabrication process is also stressed in that the strip of mask between the pads is designed narrower, the alignment of the mask to copper becomes more critical
Technical Library | 2015-02-19 16:54:34.0
Pad cratering is an important failure mode besides crack of solder joint as it’ll pass the regular test but have impact on the long term reliability of the product. A new pin pull test method with solder ball attached and positioning the test board at an angle of 30º is employed to study the strength of pad cratering. This new method clearly reveals the failure mechanism. And a proper way to interpret the finite element analysis (FEA) result is discussed. Impact of pad dimension, width and angle of copper trace on the strength is included. Some findings not included in previous research could help to guide the design for better performance
Technical Library | 2021-05-26 00:53:26.0
This paper describes a copper electroplating enabling technology for filling microvias. Driven by the need for faster, smaller and higher performance communication and electronic devices, build-up technology incorporating microvias has emerged as a viable multilayer printed circuit manufacturing technology. Increased wiring density, reduced line widths, smaller through-holes and microvias are all attributes of these High Density Interconnect (HDI) packages. Filling the microvias with conductive material allows the use of stacked vias and via in pad designs thereby facilitating additional packaging density. Other potential design attributes include thermal management enhancement and benefits for high frequency circuitry. Electrodeposited copper can be utilized for filling microvias and provides potential advantages over alternative via plugging techniques. The features, development, scale up and results of direct current (DC) and periodic pulse reverse (PPR) acid copper via filling processes, including chemistry and equipment, are described.
Technical Library | 2021-07-06 21:20:38.0
The evolution of internet-enabled mobile devices has driven innovation in the manufacturing and design of technology capable of high-frequency electronic signal transfer. Among the primary factors affecting the integrity of high-frequency signals is the surface finish applied on PCB copper pads – a need commonly met through the electroless nickel immersion gold process, ENIG. However, there are well-documented limitations of ENIG due to the presence of nickel, the properties of which result in an overall reduced performance in high-frequency data transfer rate for ENIG-applied electronics, compared to bare copper.
Technical Library | 2020-08-05 18:49:32.0
The evolution of internet-enabled mobile devices has driven innovation in the manufacturing and design of technology capable of high-frequency electronic signal transfer. Among the primary factors affecting the integrity of high-frequency signals is the surface finish applied on PCB copper pads – a need commonly met through the electroless nickel immersion gold process, ENIG. However, there are well-documented limitations of ENIG due to the presence of nickel, the properties of which result in an overall reduced performance in high-frequency data transfer rate for ENIG-applied electronics, compared to bare copper. An innovation over traditional ENIG is a nickel-less approach involving a special nano-engineered barrier designed to coat copper contacts, finished with an outermost gold layer. In this paper, assemblies involving this nickel-less novel surface finish have been subjected to extended thermal exposure, then intermetallics analyses, contact/sheet resistance comparison after every reflow cycle (up to 6 reflow cycles) to assess the prevention of copper atoms diffusion into gold layer, solder ball pull and shear tests to evaluate the aging and long-term reliability of solder joints, and insertion loss testing to gauge whether this surface finish can be used for high-frequency, high density interconnect (HDI) applications.
Technical Library | 2018-01-17 22:47:02.0
Fine pitch copper (Cu) Pillar bump has been growing adoption in high performance and low-cost flip chip packages. Higher input/output (I/O) density and very fine pitch requirements are driving very small feature sizes such as small bump on a narrow pad or bond-on-lead (BOL) interconnection, while higher performance requirements are driving increased current densities, thus assembling such packages using a standard mass reflow (MR) process and maintaining its performance is a real and serious challenge. (...) In this study a comprehensive finding on the assembly challenges, package design, and reliability data will be published. Originally published in the SMTA International 2016
Technical Library | 2023-08-04 15:27:30.0
A designed experiment evaluated the influence of several variables on appearance and strength of Pb-free solder joints. Components, with leads finished with nickel-palladium-gold (NiPdAu), were used from Texas Instruments (TI) and two other integrated circuit suppliers. Pb-free solder paste used was tin-silver-copper (SnAgCu) alloy. Variables were printed wiring board (PWB) pad size/stencil aperture (the pad finish was consistent; electrolysis Ni/immersion Au), reflow atmosphere, reflow temperature, Pd thickness in the NiPdAu finish, and thermal aging. Height of solder wetting to component lead sides was measured for both ceramic plate and PWB soldering. A third response was solder joint strength; a "lead pull" test determined the maximum force needed to pull the component lead from the PWB. This paper presents a statistical analysis of the designed experiment. Reflow atmosphere and pad size/stencil aperture have the greatest contribution to the height of lead side wetting. Reflow temperature, palladium thickness, and preconditioning had very little impact on side-wetting height. For lead pull, variance in the data was relatively small and the factors tested had little impact.
Technical Library | 2024-07-24 01:04:35.0
Quad Flat No Leads (QFN) package designs receive more and more attention in electronic industry recently. This package offers a number of benefits including (1) small size, such as a near die size footprint, thin profile, and light weight; (2) easy PCB trace routing due to the use of perimeter I/O pads; (3) reduced lead inductance; and (4) good thermal and electrical performance due to the adoption of exposed copper die-pad technology. These features make the QFN an ideal choice for many new applications where size, weight, electrical, and thermal properties are important. However, adoption of QFN often runs into voiding issue at SMT assembly. Upon reflow, outgassing of solder paste flux at the large thermal pad has difficulty escaping and inevitably results in voiding. It is well known that the presence of voids will affect the mechanical properties of joints and deteriorate the strength, ductility, creep, and fatigue life. In addition, voids could also produce spot overheating, lessening the reliability of the joints.
Technical Library | 2020-07-15 18:29:34.0
In the early 2000s the first fine-pitch ball grid array devices became popular with designers looking to pack as much horsepower into as small a space as possible. "Smaller is better" became the rule and with that the mechanical drilling world became severely impacted by available drill bit sizes, aspect ratios, and plating methodologies. First of all, the diameter of the drill needed to be in the 0.006" or smaller range due to the reduction of pad size and spacing pitch. Secondly, the aspect ratio (depth to diameter) became limited by drill flute length, positional accuracy, rigidity of the tools (to prevent breakage), and the throwing power of acid copper plating systems. And lastly, the plating needed to close up the hole as much as possible, which led to problems with voiding, incomplete fill, and gas/solution entrapment.