Technical Library | 2024-06-23 21:57:16.0
Two extremes of reflow time scale for copper pillar flip chip solder joints were explored in this study. Sn-2.5Ag solder capped pillars were joined to laminate substrates using either conventional forced convection reflow or the controlled impingement of a defocused infrared laser. The laser reflow joining process was accomplished with an order of magnitude reduction in time above liquidus and a similar increase in solidification cooling rate. The brief reflow time and rapid cooling of a laser impingement reflow necessarily affects all time and temperature dependent phenomena characteristic of reflowed molten solder. These include second phase precipitate dissolution, base metal (copper) dissolution, and the extent of surface wetting. This study examines the reflow dependent microstructural aspects of flip chip Sn-Ag joints on samples of two different size scales, the first with copper pillars of 70μm diameter on 120μm pitch and the second with 23μm diameter pillars on a 40μm pitch. The length scale of Pb-free solder joints is known to affect the Sn grain solidification structure; Sn grain morphology will be noted across both reflow time and joint length scales. Sn grain morphology was further found to be dependent on the extent of surface wetting when such wetting circumvented the copper diffusion barrier layer. Microstructural analysis also will include a comparison of intermetallic structures formed; including the size and number density of second phase Ag3Sn precipitates in the joint and the morphology and thickness of the interfacial intermetallics formed on the pillar and substrate surfaces.
Technical Library | 2018-01-17 22:47:02.0
Fine pitch copper (Cu) Pillar bump has been growing adoption in high performance and low-cost flip chip packages. Higher input/output (I/O) density and very fine pitch requirements are driving very small feature sizes such as small bump on a narrow pad or bond-on-lead (BOL) interconnection, while higher performance requirements are driving increased current densities, thus assembling such packages using a standard mass reflow (MR) process and maintaining its performance is a real and serious challenge. (...) In this study a comprehensive finding on the assembly challenges, package design, and reliability data will be published. Originally published in the SMTA International 2016
Technical Library | 2015-12-02 18:32:50.0
(Thermal Compression with Non-Conductive Paste Underfill) Method.The companies writing this paper have jointly developed Copper (Cu) Pillar micro-bump and TCNCP(Thermal Compression with Non-Conductive Paste) technology over the last two+ years. The Cu Pillar micro-bump and TCNCP is one of the platform technologies, which is essentially required for 2.5D/3D chip stacking as well as cost effective SFF (small form factor) package enablement.Although the baseline packaging process methodology for a normal pad pitch (i.e. inline 50μm) within smaller chip size (i.e. 100 mm2) has been established and are in use for HVM production, there are several challenges to be addressed for further development for commercialization of finer bump pitch with larger die (i.e. ≤50μm tri-tier bond pad with the die larger than 400mm2).This paper will address the key challenges of each field, such as the Cu trace design on a substrate for robust micro-joint reliability, TCNCP technology, and substrate technology (i.e. structure, surface finish). Technical recommendations based on the lessons learned from a series of process experimentation will be provided, as well. Finally, this technology has been used for the successful launching of the company FPGA products with SFF packaging technology.
Technical Library | 2019-07-17 17:56:34.0
The increased demand for electronic devices in recent years has led to an extensive research in the field to meet the requirements of the industry. Electrolytic copper has been an important technology in the fabrication of PCBs and semiconductors. Aqueous sulfuric acid baths are explored for filling or building up with copper structures like blind micro vias (BMV), trenches, through holes (TH), and pillar bumps. As circuit miniaturization continues, developing a process that simultaneously fills vias and plates TH with various sizes and aspect ratios, while minimizing the surface copper thickness is critical. Filling BMV and plating TH at the same time, presents great difficulties for the PCB manufactures. The conventional copper plating processes that provide good via fill and leveling of the deposit tend to worsen the throwing power (TP) of the electroplating bath. TP is defined as the ratio of the deposit copper thickness in the center of the through hole to its thickness at the surface. In this paper an optimization of recently developed innovative, one step acid copper plating technology for filling vias with a minimal surface thickness and plating through holes is presented.
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