Technical Library | 2012-12-20 14:36:09.0
The increased function of personal electronic devices, such as mobile phones and personal music devices, has driven the need for smaller and smaller active and passive components. This trend toward miniaturization, occurring at the same time as the conversion to RoHS-compliant lead-free assembly, has been a considerable challenge to the electronics assembly industry. The main reason for this is the higher reflow process temperatures required for Pb-free assembly. These higher temperatures can thermally damage the PCB and the components. In addition, the higher reflow temperatures can negatively affect the solder joint quality, especially when coupled with the smaller paste deposits required for these smaller components. If additional thermal processing is required, the risk increases even more. First Published at SMTA's International Conference on Soldering and Reliability in Toronto, May 2011
Technical Library | 2023-11-20 18:10:20.0
The electronics production is prone to a multitude of possible failures along the production process. Therefore, the manufacturing process of surface-mounted electronics devices (SMD) includes visual quality inspection processes for defect detection. The detection of certain error patterns like solder voids and head in pillow defects require radioscopic inspection. These high-end inspection machines, like the X-ray inspection, rely on static checking routines, programmed manually by the expert user of the machine, to verify the quality. The utilization of the implicit knowledge of domain expert(s), based on soldering guidelines, allows the evaluation of the quality. The distinctive dependence on the individual qualification significantly influences false call rates of the inbuilt computer vision routines. In this contribution, we present a novel framework for the automatic solder joint classification based on Convolutional Neural Networks (CNN), flexibly reclassifying insufficient X-ray inspection results. We utilize existing deep learning network architectures for a region of interest detection on 2D grayscale images. The comparison with product-related meta-data ensures the presence of relevant areas and results in a subsequent classification based on a CNN. Subsequent data augmentation ensures sufficient input features. The results indicate a significant reduction of the false call rate compared to commercial X-ray machines, combined with reduced product-related optimization iterations.
Technical Library | 2024-07-24 01:04:35.0
Quad Flat No Leads (QFN) package designs receive more and more attention in electronic industry recently. This package offers a number of benefits including (1) small size, such as a near die size footprint, thin profile, and light weight; (2) easy PCB trace routing due to the use of perimeter I/O pads; (3) reduced lead inductance; and (4) good thermal and electrical performance due to the adoption of exposed copper die-pad technology. These features make the QFN an ideal choice for many new applications where size, weight, electrical, and thermal properties are important. However, adoption of QFN often runs into voiding issue at SMT assembly. Upon reflow, outgassing of solder paste flux at the large thermal pad has difficulty escaping and inevitably results in voiding. It is well known that the presence of voids will affect the mechanical properties of joints and deteriorate the strength, ductility, creep, and fatigue life. In addition, voids could also produce spot overheating, lessening the reliability of the joints.
Technical Library | 2022-10-31 17:09:04.0
The global transition to lead-free (Pb-free) electronics has led component and equipment manufacturers to transform their tin–lead (SnPb) processes to Pb-free. At the same time, Pb-free legislation has granted exemptions for some products whose applications require high long-term reliability. However, due to a reduction in the availability of SnPb components, compatibility concerns can arise if Pb-free components have to be utilized in a SnPb assembly. This compatibility situation of attaching a Pb-free component in a SnPb assembly is generally termed "backward compatibility." This paper presents the results of microstructural analysis of mixed solder joints which are formed by attaching Pb-free solder balls (SnAgCu) of a ball-grid-array component using SnPb paste. The experiment evaluates the Pb phase coarsening in bulk solder microstructure and the study of intermetallic compounds formed at the interface between the solder and the copper pad.
Technical Library | 2015-02-12 16:57:56.0
Electronic systems are known to be affected by the environmental and mechanical conditions, such as humidity, temperature, thermal shocks and vibration. These adverse environmental operating conditions, with time, could degrade the mechanical efficiency of the system and might lead to catastrophic failures.The aim of this study is to investigate the mechanical integrity of lead-free ball grid array (BGA) solder joints subjected to isothermal ageing at 150°C for up to 1000 hours. Upon ageing at 150°C the Sn-3.5Ag solder alloy initially age-softened for up to 200 hours. This behaviour was linked to the coarsening of grains. When aged beyond 200 hours the shear strength was found to increase up to 400 hours. This age-hardening was correlated with precipitation of hard Ag3Sn particles in Sn matrix. Further ageing resulted in gradual decrease in shear strength. This can be explained as the combined effect of precipitation coarsening and growth of intermetallic layer. The fractured surfaces of the broken solder balls were also investigated under a Scanning Electron Microscope. The shear failures were generally due to ductile fractures in bulk solders irrespective of the ageing time.
Technical Library | 2022-12-05 16:28:06.0
The work evaluates the impact of latent heat (LH) absorbed or released by a solder alloy during melting or solidification, respectively, on changes of dimensions of materials surrounding of the solder alloy. Our sample comprises a small printed circuit board (PCB) with a blind via filled with lead-free alloy SAC305. Differential scanning calorimetry (DSC) was employed to obtain the amount of LH per mass and a thermomechanical analyzer was used to measure the thermally induced deformation. A plateau during melting and a peak during solidification were detected during the course of dimension change. The peak height reached 1.6 μm in the place of the heat source and 0.3 μm in the distance of 3 mm from the source. The data measured during solidification was compared to a numerical model based on the finite element method. An excellent quantitative agreement was observed which confirms that the transient expansion of PCB during cooling can be explained by the release of LH from the solder alloy during solidification. Our results have important implications for the design of PCB assemblies where the contribution of recalescence to thermal stress can lead to solder joint failure.
Technical Library | 2022-10-11 20:29:31.0
Electronic assemblies deployed in harsh environments may be subjected to multiple thermal environments during the use-life of the equipment. Often the equipment may not have any macro-indicators of damage such as cracks or delamination. Quantiication of thermal environments during use-life is often not feasible because of the data-capture and storage requirements, and the overhead on core-system functionality. There is need for tools and techniques to quantify damage in deployed systems in absence of macro-indicators of damage without knowledge of prior stress history. The presented PHM framework is targeted towards high reliability applications such as avionic and space systems. In this paper, Sn3.0Ag0.5Cu alloy packages have been subjected to multiple thermal cycling environments including -55 to 125C and 0 to 100C. Assemblies investigated include area-array packages soldered on FR4 printed circuit cards. The methodology involves the use of condition monitoring devices, for gathering data on damage pre-cursors at periodic intervals. Damage-state interrogation technique has been developed based on the Levenberg-Marquardt Algorithm in conjunction with the microstructural damage evolution proxies. The presented technique is applicable to electronic assemblies which have been deployed on one thermal environment, then withdrawn from service and targeted for redeployment in a different thermal environment. Test cases have been presented to demonstrate the viability of the technique for assessment of prior damage, operational readiness and residual life for assemblies exposed to multiple thermo-mechanical environments. Prognosticated prior damage and the residual life show good correlation with experimental data, demonstrating the validity of the presented technique for multiple thermo-mechanical environments.
Technical Library | 2012-12-13 21:20:05.0
First published in the 2012 IPC APEX EXPO technical conference proceedings. We investigated the micro-void formation of solder joints after reliability tests such as preconditioning (precon) and thermal cycle (TC) by varying the thickness of Palladium (Pd) in Electroless Nickel / Electroless Palladium / Immersion Gold (ENEPIG) surface finish. We used lead-free solder of Sn-1.2Ag-0.5Cu-Ni (LF35). We found multiple micro-voids of less than 10 µm line up within or above the intermetallic compound (IMC) layer. The number of micro-voids increased with the palladium (Pd) layer thickness. Our results revealed that the micro-void formation should be related to (Pd, Ni)Sn4 phase resulted from thick Pd layer. We propose that micro-voids may form due to either entrapping of volatile gas by (Pd, Ni)Sn4 or creeping of (Pd, Ni)Sn4.
Technical Library | 2013-12-27 10:39:21.0
The head-in-pillow defect has become a relatively common failure mode in the industry since the implementation of Pb-free technologies, generating much concern. A head-in-pillow defect is the incomplete wetting of the entire solder joint of a Ball-Grid Array (BGA), Chip-Scale Package (CSP), or even a Package-On-Package (PoP) and is characterized as a process anomaly, where the solder paste and BGA ball both reflow but do not coalesce. When looking at a cross-section, it actually looks like a head has pressed into a soft pillow. There are two main sources of head-in-pillow defects: poor wetting and PWB or package warpage. Poor wetting can result from a variety of sources, such as solder ball oxidation, an inappropriate thermal reflow profile or poor fluxing action. This paper addresses the three sources or contributing issues (supply, process & material) of the head-in-pillow defects. It will thoroughly review these three issues and how they relate to result in head-in pillow defects. In addition, a head-in-pillow elimination plan will be presented with real life examples will be to illustrate these head-in-pillow solutions.
Technical Library | 2017-02-28 12:39:50.0
During the last 5 years mobile phones and other portable consumer electronics have been extremely popular and spread all over the world in different climate zones in very high volumes. At the same time the mobile phone terminal for many people has become a necessity that is brought with them in any activity they practice. These changes in user behavior have heavily changed the impact on handheld terminals from moisture, sweat, corrosive atmospheres and mechanical drop. As a result of this the requirement to solder joint reliability, corrosion stability and wear resistance are heavily increasing to keep a high reliability of the terminal.Immersion Ni/Au has been the overall dominant surface finish on Printed Wiring Boards (PWB's) for the last 10 years, but a paradigm shift to avoid use of this thin and porous surface finish is ongoing nowadays because it can’t address these challenges in a satisfactory way.In today's handheld terminals, Organic Solder Preservative (OSP) has replaced Immersion Ni/Au on solder pads. Carbon surface finish for Key- and spring contact-pads, combined with the right concept design can make use of Immersion Ni/Au unnecessary in the near future. The result will be higher reliability with less expensive and simpler processes.This paper will discuss the various considerations for choice of surface finish and results from the feasibility studies performed.
