Technical Library: defect (Page 7 of 14)

True Height Measurement in Solder Paste Inspection

Technical Library | 2015-04-29 03:48:39.0

SPI equipment is routinely used in Printed Circuit Board (PCB) manufacturing to monitor and control one of the most crucial steps affecting the finished quality of circuit board. Solder paste deposition is the key process in board assembly operations using SMT techniques. Our LSM™ system was the industry's first popular method of manually inspecting solder paste; our SE systems revolutionized SMT production by offering an automated method for performing in-process 3D inspection on the assembly line. SPI systems measure the height and volume of the solder pads before the components are applied and the solder melted, and when used properly, can reduce the incidence of solder-related defects to statistically insignificant amounts. Critical to the SPI measurement is the accuracy of the height measurement because that has a direct correlation with solder volume and defects.

CyberOptics Corporation

NSOP Reduction for QFN RFIC Packages

Technical Library | 2017-08-31 13:43:48.0

Wire bonded packages using conventional copper leadframe have been used in industry for quite some time. The growth of portable and wireless products is driving the miniaturization of packages resulting in the development of many types of thin form factor packages and cost effective assembly processes. Proper optimization of wire bond parameters and machine settings are essential for good yields. Wire bond process can generate a variety of defects such as lifted bond, cracked metallization, poor intermetallic etc. NSOP – non-stick on pad is a defect in wire bonding which can affect front end assembly yields. In this condition, the imprint of the bond is left on the bond pad without the wire being attached. NSOP failures are costly as the entire device is rejected if there is one such failure on any bond pad. The paper presents some of the failure modes observed and the efforts to address NSOP reduction

Peregrine Semiconductor

Improve SMT Assembly Yields Using Root Cause Analysis in Stencil Design

Technical Library | 2018-07-18 16:28:26.0

Reduction of first pass defects in the SMT assembly process minimizes cost, assembly time and improves reliability. These three areas, cost, delivery and reliability determine manufacturing yields and are key in maintaining a successful and profitable assembly process. It is commonly accepted that the solder paste printing process causes the highest percentage of yield challenges in the SMT assembly process. As form factor continues to get smaller, the challenge to obtain 100% yield becomes more difficult.This paper will identify defects affecting SMT yields in the printing process and discuss their Root Cause. Outer layer copper weight and surface treatment will also be addressed as to their effect on printability. Experiments using leadless and emerging components will be studied and root cause analysis will be presented

FCT ASSEMBLY, INC.

Using Rheology Measurement As A Potentially Predictive Tool For Solder Paste Transfer Efficiency And Print Volume Consistency

Technical Library | 2020-07-02 13:29:37.0

Industry standards such as J-STD-005 and JIS Z 3284-1994 call for the use of viscosity measurement(s) as a quality assurance test method for solder paste. Almost all solder paste produced and sold use a viscosity range at a single shear rate as part of the pass-fail criteria for shipment and customer acceptance respectively. As had been reported many times, an estimated 80% of the defects associated with the surface mount technology process involve defects created during the printing process. Viscosity at a single shear rate could predict a fatal flaw in the printability of a solder paste sample. However, false positive single shear rate viscosity readings are not unknown.

Alpha Assembly Solutions

Defect freeQFN Assembly

Technical Library | 2011-06-09 20:28:30.0

QFN Description: A QFN package is a QUAD-FLAT-NO LEAD device. This package is small and lightweight and has no leads (unlike a gull wing or J-leaded device). QFN’s have a thermal pad (paddle) on the bottom side of the part that offers heat dissipation and

AccuSpec Electronics, LLC

Detection of Bare PCB Defects by Image Subtraction Method using Machine Vision

Technical Library | 2011-08-11 20:06:48.0

(Proceedings of the World Congress on Engineering 2011) A Printed Circuit Board (PCB) consists of circuit with electronic components mounted on surface. There are three main steps involved in manufacturing process, where the inspection of PCB is necessar

Sant Longowal Institute of Engineering and Technology (SLIET)

Lead-free SMT Soldering Defects How to Prevent Them

Technical Library | 2012-10-23 14:25:38.0

Tin-Silver-Copper alloys are the primary choice for lead-free SMT assembly. Although there are other options available such as alloys containing bismuth or indium and other elements, tin-silver-copper solders, also known as SAC alloys are by far the most popular. They are used by approximately 65% of users, as last surveyed by Soldertec in 2003.

Kester

Conformal Coating Defects

Technical Library | 2023-07-04 17:31:22.0

Conformal Coatings are polymeric materials used to protect circuitry, parts, and related components. They are most commonly used to protect printed circuit boards (PCBs) and electronic devices. However, conformal coatings can be applied to a wide variety of materials, including metal, plastic, silicone, ceramics, glass, and even paper. We use the term "substrate" to refer to an object or material that's been coated with a conformal coating.

Diamond MT

Flex Crack Mitigation

Technical Library | 2008-10-23 15:36:58.0

As part of continuous process improvement at KEMET, most failure modes caused by the capacitor manufacturing process have been systematically eliminated. Today these capacitor manufacturing-related defects are now at a parts per billion (PPB) level. Pareto analysis of customer complaints indicates that the #1 failure mode is IR failure due to flex cracks.

KEMET Electronics Corporation

21st Century Semiconductor Manufacturing Capabilities

Technical Library | 1999-05-06 14:44:11.0

Semiconductor device manufacturers face many difficult challenges as we enter the 21st century. Some are direct consequences of adherence to Gordon Moore's Law, which states that device complexity doubles about every 18 months. Feature size reduction, increased wafer diameter, increased chip size, ultra-clean processing, and defect reduction among others are manifestations that have a direct bearing on the cost and quality of products, factory flexibility in responding to changing technology or business conditions, and on the timelines of product delivery to the ultimate customer.

Intel Corporation


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