Technical Library: defect analysis (Page 1 of 2)

INTELLI-Pro -- The Future of Automated Optical Inspection

Technical Library | 2022-06-27 17:04:51.0

In today's Electronics Manufacturing Industry, standards for defect and quality control are stricter than ever due to advancements of electronic products and increasing safety and environmental regulations. Electronics Manufacturers are forced to maximize their production efficiency by implementing lean manufacturing initiatives and optimizing production processes. With this in mind, manufacturers are relying upon Automated Optical Inspection (AOI) equipment to streamline the manufacturing process and provide real time root cause analysis of manufacturing defects. The objective is to increase profitability by improving production yields and reducing costly rework.

MIRTEC Corp

Micro-Sectioning of PCBs for Failure Analysis

Technical Library | 2010-01-13 12:34:10.0

Micro-sectioning (sometimes referred to as cross-sectioning)is a technique, used to characterize materials or to perform a failure mode analysis, for exposing an internal section of a PCB or package. Destructive in nature, cross-sectioning requires encapsulation of the specimen in order to provide support, stability, and protection. Failures that can be investigated through micro-sectional analysis include component defects, thermo-mechanical failures, processing failures related to solder reflow, opens or shorts, voiding and raw material evaluations.

BEST Inc.

Projection Moiré vs. Shadow Moiré for Warpage Measurement and Failure Analysis of Advanced Packages

Technical Library | 2013-01-31 18:43:15.0

There are three key industry trends that are driving the need for temperature-dependent warpage measurement: the trend toward finer-pitch devices, the emergence of lead-free processing, and changes in device form factors. Warpage measurement has become a key measurement for analysis; prevention and prediction of interconnect defects and has been employed in failure analysis labs and production sites worldwide. First published in the 2012 IPC APEX EXPO technical conference proceedings

ZN Technologies

A PROCEDURE TO DETERMINE HEAD-IN-PILLOW DEFECT AND ANALYSIS OF CONTRIBUTING FACTORS

Technical Library | 2020-07-02 01:14:44.0

Head-in-Pillow (HIP) defects are a growing concern in the electronics industry. These defects are usually believed to be the result of several factors, individually or in combination. Some of the major contributing factors include: surface quality of the BGA spheres, activity of the paste flux, improper placement / misalignment of the components, a non-optimal reflow profile, and warpage of the components. To understand the role of each of these factors in producing head-in-pillow defects and to find ways to mitigate them, we have developed two in-house tests.

Cookson Electronics

Bare PCB inspection for Track cut, Track Short and Pad Damage using simple Image Processing Operations

Technical Library | 2021-05-06 13:48:05.0

In this paper most commonly occurring Bare PCB defects such as Track Cut, Track short and Pad Damages are detected by Image processing techniques. Reference PCB without having any defects is compared with test PCB having defects to identify the defects and x-y coordinates of the center of the defects along with radii are obtained using Difference of Gaussian method and location of the individual type of defects are marked either by similar color or different colors. Result Analysis includes time taken for the inspection of a single defect, multiple similar defects, and multiple different defects. Time taken is ranging from 1.674 to 1.714 seconds if the individual type of defects are marked by different colors and 0.670 to 0.709 seconds if all the identified defects are marked by the same colors.

Vidya Vikas Institute Of Engineering And Technology

Flex Crack Mitigation

Technical Library | 2008-10-23 15:36:58.0

As part of continuous process improvement at KEMET, most failure modes caused by the capacitor manufacturing process have been systematically eliminated. Today these capacitor manufacturing-related defects are now at a parts per billion (PPB) level. Pareto analysis of customer complaints indicates that the #1 failure mode is IR failure due to flex cracks.

KEMET Electronics Corporation

Advanced Second Level Assembly Analysis Techniques - Troubleshooting Head-In-Pillow, Opens, and Shorts with Dual Full-Field 3D Surface Warpage Data Sets/

Technical Library | 2014-08-19 16:04:28.0

SMT assembly planning and failure analysis of surface mount assembly defects often include component warpage evaluation. Coplanarity values of Integrated Circuit packages have traditionally been used to establish pass/fail limits. As surface mount components become smaller, with denser interconnect arrays, and processes such package-on-package assembly become prevalent, advanced methods using dual surface full-field data become critical for effective Assembly Planning, Quality Assurance, and Failure Analysis. A more complete approach than just measuring the coplanarity of the package is needed. Analyzing the gap between two surfaces that are constantly changing during the reflow thermal cycle is required, to effectively address the challenges of modern SMT assembly.

Akrometrix

Progressive Failure Analysis of Laminates with Embedded Wrinkle Defects Based on an Elastoplastic Damage Model

Technical Library | 2021-03-04 15:16:27.0

Out-of-plane wrinkling has a significant influence on the mechanical performance of composite laminates. Numerical simulations were conducted to investigate the progressive failure behavior of fiber-reinforced composite laminates with out-of-plane wrinkle defects subjected to axial compression. To describe the material degradation, a three-dimensional elastoplastic damage model with four damage modes (i.e., fiber tensile failure, matrix failure, fiber kinking/splitting, and delamination) was developed based on the LaRC05 criterion. To improve the computational efficiency in searching for the fracture angle in the matrix failure analysis, a high-efficiency and robust modified algorithm that combines the golden section search method with an inverse interpolation based on an existing study is proposed.

Jinan University

Overview of Quality and Reliability Issues in the National Technology Roadmap for Semiconductors

Technical Library | 1999-08-05 10:27:43.0

This document is an update to the 1994 Quality and Reliability Roadmap issued in support of the 1994 National Technology Roadmap for Semiconductors. This report revisits the challenges, constraints, priorities, and research needs pertaining to quality and reliability issues. It also provides key project proposals that must be implemented to address concerns about reliability attainment and defect learning. An expanded section on test-to-test, diagnostics, and failure analysis; an edited version of the Product Analysis Forum Roadmap; and an appendix containing a draft report highlighting reliability issues is included.

SEMATECH

Industry 4.0: Mining Physical Defects in Production of Surface-Mount Devices

Technical Library | 2021-12-02 01:44:00.0

With the advent of Industry 4.0, production processes have been endowed with intelligent cyber-physical systems generating massive amounts of streaming sensor data. Internet of Things technologies have enabled capturing, managing, and processing production data at a large scale in order to utilize this data as an asset for the optimization of production processes. In this work, we focus on the automatic detection of physical defects in the production of surfacemount devices. We show how to build a classification model based on random forests that efficiently detects defect products with a high degree of precision. In fact, the results of our preliminary experimental analysis indicate that our approach is able to correctly determine defects in a simulated production environment of surface-mount devices with a MCC score of 0.96. We investigate the feasibility of utilizing this approach in realistic settings. We believe that our approach will help to advance the production of surface-mount devices.

Fraunhofer Institute for Applied Information Technology

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