Technical Library | 2016-11-30 21:30:50.0
Mid-chip solder balling is a defect typically associated with solder paste exhibiting poor hot slump and/or insufficient wetting during the reflow soldering process, resulting in paste flowing under the component or onto the solder resist. Once molten, this solder is compressed and forced to the side of the component, causing mid-chip solder balling.This paper documents the experimental work performed to further understand the impact on mid-chip solder balling from both the manufacturing process and the flux chemistry.
Technical Library | 2020-08-05 18:49:32.0
The evolution of internet-enabled mobile devices has driven innovation in the manufacturing and design of technology capable of high-frequency electronic signal transfer. Among the primary factors affecting the integrity of high-frequency signals is the surface finish applied on PCB copper pads – a need commonly met through the electroless nickel immersion gold process, ENIG. However, there are well-documented limitations of ENIG due to the presence of nickel, the properties of which result in an overall reduced performance in high-frequency data transfer rate for ENIG-applied electronics, compared to bare copper. An innovation over traditional ENIG is a nickel-less approach involving a special nano-engineered barrier designed to coat copper contacts, finished with an outermost gold layer. In this paper, assemblies involving this nickel-less novel surface finish have been subjected to extended thermal exposure, then intermetallics analyses, contact/sheet resistance comparison after every reflow cycle (up to 6 reflow cycles) to assess the prevention of copper atoms diffusion into gold layer, solder ball pull and shear tests to evaluate the aging and long-term reliability of solder joints, and insertion loss testing to gauge whether this surface finish can be used for high-frequency, high density interconnect (HDI) applications.
Technical Library | 2019-07-23 22:33:47.0
The Quad Flat Pack No Leads (QFN) style of leadless packaging [also known as a Land Grid Array (LGA)] is rapidly increasing in us e for wireless, automotive, telecom and many other areas becaus e of its low cost, low stand-off height and excellent thermal and electri cal properties. With the implementation of any new package type, there is always a learning curve for its use in design and processing as well as for the Process and Quality Engineers who have to get to grips with the challenges that these packages bring. Therefore, this paper will provide examples of the common process defects that can be seen with QFNs /LGAs when using optical and x-ray inspection as part of manufacturing quality control. Results of trials conducted on four PCB finishes and using vapour phase and convection reflow will be discussed.
Technical Library | 2013-03-27 23:43:40.0
Vapor phase, once cast to the annals’ of history is making a comeback. Why? Reflow technology is well developed and has served the industry for many years, it is simple and it is consistent. All points are true – when dealing with the centre section of the bell curve. Today’s PCB manufacturers are faced with many designs which no longer fall into that polite category but rather test the process engineering groups with heavier and larger panels, large ground planes located in tricky places, component mass densities which are poorly distributed, ever changing Pb Free alloys and higher process temperatures. All the time the costs for the panels increase, availability of “process trial” boards diminishes and yields are expected to be extremely high with zero scrap rates. The final process in the assembly line has the capacity to secure all the value of the assembly or destroy it. If a panel is poorly soldered due to poor Oven setup or incorrect programming of the profile the recovery of the panel is at best expensive, at worst a loss. For these challenges people are turning to Vapor Phase.
Technical Library | 2014-08-19 16:04:28.0
SMT assembly planning and failure analysis of surface mount assembly defects often include component warpage evaluation. Coplanarity values of Integrated Circuit packages have traditionally been used to establish pass/fail limits. As surface mount components become smaller, with denser interconnect arrays, and processes such package-on-package assembly become prevalent, advanced methods using dual surface full-field data become critical for effective Assembly Planning, Quality Assurance, and Failure Analysis. A more complete approach than just measuring the coplanarity of the package is needed. Analyzing the gap between two surfaces that are constantly changing during the reflow thermal cycle is required, to effectively address the challenges of modern SMT assembly.
Technical Library | 2020-04-01 23:32:29.0
Low temperature solder alloys are preferred for the assembly of temperature-sensitive components and substrates. The alloys in this category are required to reflow between 170 and 200oC soldering temperatures. Lower soldering temperatures result in lower thermal stresses and defects, such as warping during assembly, and permit use of lower cost substrates. Sn-Bi alloys have lower melting temperatures, but some of its performance drawbacks can be seen as deterrent for its use in electronics devices.Here we show that non-eutectic Sn-Bi alloys can be used to improve these properties and further align them with the electronics industry specific needs. The physical properties and drop shock performance of various alloys are evaluated, and their results are analysed in terms of the alloy composition, including Bi content and alloying additions.
Technical Library | 2019-05-01 23:18:27.0
Moisture can accelerate various failure mechanisms in printed circuit board assemblies. Moisture can be initially present in the epoxy glass prepreg, absorbed during the wet processes in printed circuit board manufacturing, or diffuse into the printed circuit board during storage. Moisture can reside in the resin, resin/glass interfaces, and micro-cracks or voids due to defects. Higher reflow temperatures associated with lead-free processing increase the vapor pressure, which can lead to higher amounts of moisture uptake compared to eutectic tin-lead reflow processes. In addition to cohesive or adhesive failures within the printed circuit board that lead to cracking and delamination, moisture can also lead to the creation of low impedance paths due to metal migration, interfacial degradation resulting in conductive filament formation, and changes in dimensional stability. Studies have shown that moisture can also reduce the glass-transition temperature and increase the dielectric constant, leading to a reduction in circuit switching speeds and an increase in propagation delay times. This paper provides an overview of printed circuit board fabrication, followed by a brief discussion of moisture diffusion processes, governing models, and dependent variables. We then present guidelines for printed circuit board handling and storage during various stages of production and fabrication so as to mitigate moisture-induced failures.
Technical Library | 2020-09-23 21:37:25.0
The need to minimise thermal damage to components and laminates, to reduce warpage-induced defects to BGA packages, and to save energy, is driving the electronics industry towards lower process temperatures. For soldering processes the only way that temperatures can be substantially reduced is by using solders with lower melting points. Because of constraints of toxicity, cost and performance, the number of alloys that can be used for electronics assembly is limited and the best prospects appear to be those based around the eutectic in the Bi-Sn system, which has a melting point of about 139°C. Experience so far indicates that such Bi-Sn alloys do not have the mechanical properties and microstructural stability necessary to deliver the reliability required for the mounting of BGA packages. Options for improving mechanical properties with alloying additions that do not also push the process temperature back over 200°C are limited. An alternative approach that maintains a low process temperature is to form a hybrid joint with a conventional solder ball reflowed with a Bi-Sn alloy paste. During reflow there is mixing of the ball and paste alloys but it has been found that to achieve the best reliability a proportion of the ball alloy has to be retained in the joint, particular in the part of the joint that is subjected to maximum shear stress in service, which is usually the area near the component side. The challenge is then to find a reproducible method for controlling the fraction of the joint thickness that remains as the original solder ball alloy. Empirical evidence indicates that for a particular combination of ball and paste alloys and reflow temperature the extent to which the ball alloy is consumed by mixing with the paste alloy is dependent on the volume of paste deposited on the pad. If this promising method of achieving lower process temperatures is to be implemented in mass production without compromising reliability it would be necessary to have a method of ensuring the optimum proportion of ball alloy left in the joint after reflow can be consistently maintained. In this paper the author explains how the volume of low melting point alloy paste that delivers the optimum proportion of retained ball alloy for a particular reflow temperature can be determined by reference to the phase diagrams of the ball and paste alloys. The example presented is based on the equilibrium phase diagram of the binary Bi-Sn system but the method could be applied to any combination of ball and paste alloys for which at least a partial phase diagram is available or could be easily determined.
Technical Library | 2019-10-03 14:27:01.0
Knowing how package warpage changes over temperature is a critical variable in order to assemble reliable surface mount attached technology. Component and component or component and board surfaces must stay relatively flat with one another or surface mount defects, such as head-in-pillow, open joints, bridged joints, stretched joints, etc. may occur. Initial package flatness can be affected by numerous aspects of the component manufacturing and design. However, change in shape over temperature is primarily driven by CTE mismatch between the different materials in the package. Thus material CTE is a critical factor in package design. When analyzing or modeling package warpage, one may assume that the package receives heat evenly on all sides, when in production this may not be the case. Thus, in order to understand how temperature uniformity can affect the warpage of a package, a case study of package warpage versus different heating spreads is performed.Packages used in the case study have larger form factors, so that the effect of non-uniformity can be more readily quantified within each package. Small and thin packages are less prone to issues with package temperature variation, due to the ability for the heat to conduct through the package material and make up for uneven sources of heat. Multiple packages and multiple package form factors are measured for warpage via a shadow moiré technique while being heated and cooled through reflow profiles matching real world production conditions. Heating of the package is adjusted to compare an evenly heated package to one that is heated unevenly and has poor temperature uniformity between package surfaces. The warpage is measured dynamically as the package is heated and cooled. Conclusions are drawn as to how the role of uneven temperature spread affects the package warpage.
Technical Library | 2020-07-08 20:05:59.0
There is a compelling need for functional testing of high-speed input/output signals on circuit boards ranging from 1 gigabit per second (Gbps) to several hundred Gbps. While manufacturing tests such as Automatic Optical Inspection (AOI) and In-Circuit Test (ICT) are useful in identifying catastrophic defects, most high-speed signals require more scrutiny for failure modes that arise due to high-speed conditions, such as jitter. Functional ATE is seldom fast enough to measure high-speed signals and interpret results automatically. Additionally, to measure these adverse effects it is necessary to have the tester connections very close to the unit under test (UUT) as lead wires connecting the instruments can distort the signal. The solution we describe here involves the use of a field programmable gate array (FPGA) to implement the test instrument called a synthetic instrument (SI). SIs can be designed using VHDL or Verilog descriptions and "synthesized" into an FPGA. A variety of general-purpose instruments, such as signal generators, voltmeters, waveform analyzers can thus be synthesized, but the FPGA approach need not be limited to instruments with traditional instrument equivalents. Rather, more complex and peculiar test functions that pertain to high-speed I/O applications, such as bit error rate tests, SerDes tests, even USB 3.0 (running at 5 Gbps) protocol tests can be programmed and synthesized within an FPGA. By using specific-purpose test mechanisms for high-speed I/O the test engineer can reduce test development time. The synthetic instruments as well as the tests themselves can find applications in several UUTs. In some cases, the same test can be reused without any alteration. For example, a USB 3.0 bus is ubiquitous, and a test aimed at fault detection and diagnoses can be used as part of the test of any UUT that uses this bus. Additionally, parts of the test set may be reused for testing another high-speed I/O. It is reasonable to utilize some of the test routines used in a USB 3.0 test, in the development of a USB 3.1 (running at 10 Gbps), even if the latter has substantial differences in protocol. Many of the SI developed for one protocol can be reused as is, while other SIs may need to undergo modifications before reuse. The modifications will likely take less time and effort than starting from scratch. This paper illustrates an example of high-speed I/O testing, generalizes failure modes that are likely to occur in high-speed I/O, and offers a strategy for testing them with SIs within FPGAs. This strategy offers several advantages besides reusability, including tester proximity to the UUT, test modularization, standardization approaching an ATE-agnostic test development process, overcoming physical limitations of general-purpose test instruments, and utilization of specific-purpose test instruments. Additionally, test instrument obsolescence can be overcome by upgrading to ever-faster and larger FPGAs without losing any previously developed design effort. With SIs and tests scalable and upward compatible, the test engineer need not start test development for high-speed I/O from scratch, which will substantially reduce time and effort.
