Technical Library | 2019-08-14 22:20:55.0
Cleanliness is a product of design, including component density, standoff height and the cleaning equipment’s ability to deliver the cleaning agent to the source of residue. The presence of manufacturing process soil, such as flux residue, incompletely activated flux, incompletely cured solder masks, debris from handling and processing fixtures, and incomplete removal of cleaning fluids can hinder the functional lifetime of the product. Contaminates trapped under a component are more problematic to failure. Advanced test methods are needed to obtain "objective evidence" for removing flux residues under leadless components.Cleaning process performance is a function of cleaning capacity and defined cleanliness. Cleaning performance can be influenced by the PCB design, cleaning material, cleaning machine, reflow conditions and a wide range of process parameters.This research project is designed to study visual flux residues trapped under the bottom termination of leadless components. This paper will research a non-destructive visual method that can be used to study the cleanability of solder pastes, cleaning material effectiveness for the soil, cleaning machine effectiveness and process parameters needed to render a clean part.
Technical Library | 2007-03-28 10:18:33.0
Legislation against the use of lead in electronics has been the driving force behind the use of lead-free solders, surface finishes, and component lead finishes. The major concern in using lead-free solders in the assembly and rework Chip Scale Packages (CSPs) is the relatively high temperatures that the components and the boards experience. Fine-pitch CSPs have very low standoff heights following assembly making inspection and rework of these components more difficult. One other concern pertinent to rework is the temperature of the neighboring components during rework. These issues, coupled with the limitations of rework equipment to handle lead-free reflow temperatures, make the task of reworking lead-free assemblies more challenging.
Technical Library | 2019-07-23 22:33:47.0
The Quad Flat Pack No Leads (QFN) style of leadless packaging [also known as a Land Grid Array (LGA)] is rapidly increasing in us e for wireless, automotive, telecom and many other areas becaus e of its low cost, low stand-off height and excellent thermal and electri cal properties. With the implementation of any new package type, there is always a learning curve for its use in design and processing as well as for the Process and Quality Engineers who have to get to grips with the challenges that these packages bring. Therefore, this paper will provide examples of the common process defects that can be seen with QFNs /LGAs when using optical and x-ray inspection as part of manufacturing quality control. Results of trials conducted on four PCB finishes and using vapour phase and convection reflow will be discussed.
Technical Library | 2020-08-27 01:22:45.0
Initially adopted internal specifications for acceptance of printed circuit boards (PCBs) used for wire bonding was that there were no nodules or scratches allowed on the wirebond pads when inspected under 20X magnification. The nodules and scratches were not defined by measurable dimensions and were considered to be unacceptable if there was any sign of a visual blemish on wire-bondable features. Analysis of the yield at a PCB manufacturer monitored monthly for over two years indicated that the target yield could not be achieved, and the main reasons for yield loss were due to nodules and scratches on the wirebonding pads. The PCB manufacturer attempted to eliminate nodules and scratches. First, a light-scrubbing step was added after electroless copper plating to remove any co-deposited fine particles that acted as a seed for nodules at the time of copper plating. Then, the electrolytic copper plating tank was emptied, fully cleaned, and filtered to eliminate the possibility of co-deposited particles in the electroplating process. Both actions greatly reduced the density of the nodules but did not fully eliminate them. Even though there was only one nodule on any wire-bonding pad, the board was still considered a reject. To reduce scratches on wirebonding pads, the PCB manufacturer utilized foam trays after routing the boards so that they did not make direct contact with other boards. This action significantly reduced the scratches on wire-bonding pads, even though some isolated scratches still appeared from time to time, which caused the boards to be rejected. Even with these significant improvements, the target yield remained unachievable. Another approach was then taken to consider if wire bonding could be successfully performed over nodules and scratches and if there was a dimensional threshold where wire bonding could be successful. A gold ball bonding process called either stand-off-stitch bonding (SSB) or ball-stitch-on-ball bonding (BSOB) was used to determine the effects of nodules and scratches on wire bonds. The dimension of nodules, including height, and the size of scratches, including width, were measured before wire bonding. Wire bonding was then performed directly on various sizes of nodules and scratches on the bonding pad, and the evaluation of wire bonds was conducted using wire pull tests before and after reliability testing. Based on the results of the wire-bonding evaluation, the internal specification for nodules and scratches for wirebondable PCBs was modified to allow nodules and scratches with a certain height and a width limitation compared to initially adopted internal specifications of no nodules and no scratches. Such an approach resulted in improved yield at the PCB manufacturer.
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