Technical Library | 1999-08-09 11:36:27.0
Shrinking process technologies and increasing design sizes continually challenge design methodologies and EDA tools to develop at an ever-increasing rate. Before the complexities of deep submicron (DSM), gate and transistor delays dominated interconnect delays, and enabled simplified design methodologies that could focus on device analysis. The advent of DSM processes is changing all of this, invalidating assumptions and approximations that existing design methodologies are based upon, and forcing design teams to re-tool. High-capacity parasitic extraction tools are now critical for successful design tape-outs.
Technical Library | 2021-08-11 00:57:57.0
This paper shows the Design and Finite Element analysis of vacuum chamber of potting machine designed for electronic ignition coil applications. There are two types of potting methods 1) With Vacuum 2) Without Vacuum.
Technical Library | 2010-12-16 16:59:09.0
This report discusses the significance of heat management in the design of printed circuit boards (PCB). After an introduction into the basics of PCBs the crucial mechanisms of heat transfer are discussed with regard to significance and typical design par
Technical Library | 2008-11-27 01:25:25.0
Military electrical connectors have traditionally used very conservative design rules that provide the ruggedization needed for harsh military use environments. Commercial electronic connectors have typically used less conservative design rules that.
Technical Library | 2012-12-14 14:17:56.0
This article provides practical and affordable Design-for- Test (DFT) and Design-for-Inspection (DFI) methods that will have a positive impact on product costs, yield, reliability, and time-to-market. The properties of testability (including controllability and observability) will be analysed as they relate to analogue and digital design rules and their cause/effect, as well as the electrical and physical characteristics of proper PCB design.
Technical Library | 2013-06-27 14:00:27.0
While IC level ESD design and the necessary protection levels are well understood, system ESD protection strategy and design efficiency have only been dealt with in an ad hoc manner. This is most obvious when we realize that a consolidated approach to system level ESD design between system manufacturers and chip suppliers has been rare. This White Paper discusses these issues in the open for the first time, and offers new and relevant insight for the development of efficient system level ESD design.
Technical Library | 1999-07-20 10:35:30.0
Circuit simulation is a necessary everyday tool to circuit designers who need to constantly verify and debug their circuits during the design process. As engineers face larger, more complex designs and tighter project schedules, fast SPICE simulation with no loss in accuracy has become a necessity. Simulation indeed accounts for a large portion of the time spent in the design and optimization of a new circuit...
Technical Library | 2001-04-24 10:47:02.0
Board-level circuits today routinely run at speeds of 100 MHz or more and are composed of dozens of complex interacting VLSI components. To design such circuits in a timely and correct manner it is necessary to pay close attention to circuit timing early in the design cycle. At fast clock speeds, managing component and interconnect propagation delay becomes a key aspect of circuit design. It is imperative that the critical paths on a circuit and the slack available for interconnect delay consumption be identified early, and drive subsequent stages in the design flow.
Technical Library | 2008-12-23 22:32:32.0
Myth 1: I don't worry about design, because most of my problems are with defects from suppliers...
Technical Library | 2008-04-22 16:57:45.0
Design workflow is the core to your design team's competitive advantage; it’s the conduit by which you turn your team's expertise and ideas into manufacturable products. And yet, all engineering teams face the challenge of maximizing their productivity within limited financial resources. How can the less-capitalized teams develop a design workflow that competes with the highly-capitalized teams? Simple: open tools.
