Technical Library | 2023-01-17 17:37:45.0
Various international market trends drive electronics manufacturers and their mate- rials and equipment suppliers to develop new assembly techniques to reduce the industry's environmental impact. Two pri- mary forces in this drive are the movements to lead-free assembly and ISO 14000 cer- tification. In response to these factors, reflow technology advances are enabling manufacturers to meet or anticipate the new environmental mandates.
Technical Library | 2023-01-17 17:19:44.0
A test program was developed to evaluate the effectiveness of vacuum reflow processing on solder joint voiding and subsequent thermal cycling performance. Area array package test vehicles were assembled using conventional reflow processing and a solder paste that generated substantial void content in the solder joints. Half of the population of test vehicles then were re-processed (reflowed) using vacuum reflow. Transmission x-ray inspection showed a significant reduction in solder voiding after vacuum processing. The solder attachment reliability of the conventional and vacuum reflowed test vehicles was characterized and compared using two different accelerated thermal cycling profiles. The thermal cycling results are discussed in terms of the general impact of voiding on solder thermal fatigue reliability, results from the open literature, and the evolving industry standards for solder voiding. Recommendations are made for further work based on other void reduction methods and additional reliability studies.
Technical Library | 2023-01-17 17:58:36.0
Heterogeneous integration has become an important performance enabler as high-performance computing (HPC) demands continue to rise. The focus to enable heterogeneous integration scaling is to push interconnect density limit with increased bandwidth and improved power efficiency. Many different advanced packaging architectures have been deployed to increase I/O wire / area density for higher data bandwidth requirements, and to enable more effective die disaggregation. Embedded Multi-die Interconnect Bridge (EMIB) technology is an advanced, cost-effective approach to in-package high density interconnect of heterogeneous chips, providing high density I/O, and controlled electrical interconnect paths between multiple dice in a package. In emerging architectures, it is required to scale down the EMIB die bump pitch in order to further increase the die-to-die (D2D) communication bandwidth. Aa a result, bump pitch scaling poses significant challenges in the plated solder bump reflow process, e.g., bump height / coplanarity control, solder wicking control, and bump void control. It's crucial to ensure a high-quality solder bump reflow process to meet the final product reliability requirements. In this paper, a combined formic acid based fluxless and vacuum assisted reflow process is developed for fine pitch plated solder bumping application. A high-volume production (HVM) ready tool has been developed for this process.
Technical Library | 2023-01-17 17:27:13.0
Reflow profile has significant impact on solder joint performance because it influences wetting and microstructure of the solder joint. The degree of wetting, the microstructure (in particular the intermetallic layer), and the inherent strength of the solder all factor into the reliability of the solder joint. This paper presents experimental results on the effect of reflow profile on both 63%Sn 37%Pb (SnPb) and 96.5%Sn 3.0%Ag 0.5%Cu (SAC 305) solder joint shear force. Specifically, the effect of the reflow peak temperature and time above solder liquidus temperature are studied. Nine reflow profiles for SAC 305 and nine reflow profiles for SnPb have been developed with three levels of peak temperature (230 o C, 240 o C, and 250 o C for SAC 305; and 195 o C, 205 o C, and 215 o C for SnPb) and three levels of time above solder liquidus temperature (30 sec., 60 sec., and 90 sec.). The shear force data of four different sizes of chip resistors (1206, 0805, 0603, and 0402) are compared across the different profiles. The shear force of the resistors is measured at time 0 (right after assembly). The fracture surfaces have been studied using a scanning electron microscopy (SEM) with energy dispersive spectroscopy (EDS)
Technical Library | 2022-01-28 02:19:23.0
This white paper provides an overview of the design and development process for the various hardware components that make up the 5G ORU white box. Whizz Systems is responsible for the electrical, thermal, mechanical engineering, and manufacturing aspects, as well as system validation and bring up of the turn key white box ORU solution.
Technical Library | 1999-08-27 09:18:58.0
A need to move beyond aerosol sprays and dipping leads to a development that answers tough requirements for controlled coverage, low waste, and environmental restrictions.
Technical Library | 2019-05-29 10:40:59.0
Design for Test or Design for Testability (DFT) can best be described as the techniques utilized to add testability features to an electronic hardware product design. These added features make it easier to develop and apply manufacturing tests to assure that the product functions correctly.
Technical Library | 2019-07-29 10:35:47.0
ACI Technologies can assist its users with process development and experimentation through the use of the conformal coating capabilities in the Demonstration Factory. Four types of coating processes are available at ACI Technologies: dip coating, manual spray coating, programmable spray coating, and manual brush application. (Manual brush application will not be discussed in this article.)
Technical Library | 2019-07-11 11:07:08.0
Affordability is not exactly the primary word which comes to mind when discussing the use of design of experiments (DOE) principles, but is generally accepted as a necessary part of the engineering activities required in the development of a product or process. However, a number of studies have indicated that the cost savings derived from a well deliberated experimental design can be substantial in the initial stages where the conditions or parameters of a process are determined. Some studies have shown a greater than 50% cost savings compared to the more conventional means of trial and error approaches to process development. At ACI Technologies (ACI), we have found the use of DOE techniques fundamental in eliminating extraneous costs otherwise spent on unnecessary testing.
Technical Library | 2019-07-01 10:44:11.0
In the electronics industry of today, companies emphasize better quality, lower cost, and shorter lead time on their products in order to keep up with their competitors. ACI Technologies (ACI) has been utilizing Computer Aided Design (CAD), Computer Aided Manufacturing(CAM), and Computer Aided Engineering (CAE) in its development of advanced electronics systems. CAD utilizes computer systems to assist in the creation, modification, analysis, and optimization of a design [1].
