Technical Library | 2013-02-07 17:01:46.0
Silicone contamination is known to have a negative impact on assembly processes such as soldering, adhesive bonding, coating, and wire bonding. In particular, silicone is known to cause de-wetting of materials from surfaces and can result in adhesive failures. There are many sources for silicone contamination with common sources being mold releases or lubricants on manufacturing tools, offgassing during cure of silicone paste adhesives, and residue from pressure sensitive tape. This effort addresses silicone contamination by quantifying adhesive effects under known silicone contaminations. The first step in this effort identified an FT-IR spectroscopic detection limit for surface silicone utilizing the area under the 1263 cm-1 (Si-CH3) absorbance peak as a function of concentration (µg/cm2). The next step was to pre-contaminate surfaces with known concentrations of silicone oil and assess the effects on surface wetting and adhesion. This information will be used to establish guidelines for silicone contamination in different manufacturing areas within Harris Corporation... First published in the 2012 IPC APEX EXPO technical conference proceedings.
Technical Library | 2008-11-06 02:17:59.0
For many years Acoustic Micro Imaging (AMI) techniques have been utilized to evaluate the quality of the underfill used to support the solder bump interconnections of Flip Chip type devices. AMI has been established as one of the few techniques that can provide reliability and quality control data, but little has been done to automate the evaluation process for Flip Chip underfill until now.
Technical Library | 2013-08-29 19:52:43.0
Au over Ni on Cu is a widely used printed circuit board (PCB) surface finish, under bump metallization (UBM), and component lead metallization. It is generally accepted that less than 3 wt.% Au in Sn-Pb solder joints inhibits formation of detrimental intermetallic compounds (IMC). However, the critical limit for Au content in Pb-free solder joints is not well established. Three surface-mount package platforms, one with a matte Sn surface finish and the others with Ni/Au finish, were soldered to Ni/Au-finished PCB using Sn-3.0Ag 0.5Cu (SAC305) solder, in a realistic manufacturing setting. The assembled boards were divided into three groups: one without any thermal treatment, one subjected to isothermal aging at 125°C for 30 days, and the third group aged at 125°C for 56 days...
Technical Library | 2023-11-27 18:29:45.0
This paper examines the modeling of viscoplastic solder behavior in the vicinity of interfacial cracking for flip chip semiconductor packages. Of particular interest is the relationship between viscoplastic deformation in the solder bumps and any possible interface cracking between the epoxy underfill layer and the silicon die. A 3-D finite element code, developed specifically for the study of interfacial fracture problems, was modified to study how viscoplastic solder material properties would affect fracture parameters such as strain energy release rate and phase angle for nearby interfacial cracks. Simplified two-layer periodic symmetry models were developed to investigate these interactions. Comparison of flip chip results using different solder material models showed that viscoplastic models yielded lower stress and fracture parameters than time independent elastic-plastic simulations. It was also found that adding second level attachment greatly increases the magnitude of the solder strain and fracture parameters. As expected, the viscoplastic and temperature dependent elastic-plastic results exhibited greater similarity to each other than results based solely on linear elastic properties. !DOI: 10.1115/1.1649242"
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