Technical Library | 2015-07-16 17:24:23.0
Qualification of electronic hardware from a corrosion resistance standpoint has traditionally relied on stressing the hardware in a variety of environments. Before the development of tests based on mixed flowing gas (MFG), hardware was typically exposed to temperature-humidity cycling. In the pre-1980s era, component feature sizes were relatively large. Corrosion, while it did occur, did not in general degrade reliability. There were rare instances of the data center environments releasing corrosive gases and corroding hardware. One that got a lot of publicity was the corrosion by sulfur-bearing gases given off by data center carpeting. More often, corrosion was due to corrosive flux residues left on as-manufactured printed circuit boards (PCBs) that led to ion migration induced electrical shorting. Ion migration induced failures also occurred inside the PCBs due to poor laminate quality and moisture trapped in the laminate layers.
Technical Library | 2020-11-29 22:02:49.0
It has been over 25 years since the earliest edition of "Everything You Ever Wanted to Know About Laminates...but Were Afraid to Ask" was pounded out on an old TRaSh-80 Computer. It has undergone periodic review and editing, including adaption for use on our website. (When I entered the industry Al Gore had not yet invented the internet.) Before I "retired" in 2004, we did another minor revision, but it was largely cosmetic, removing most references to the old military specification and introducing IPC-4101, the "new" specification for laminate and prepreg materials.
Technical Library | 2019-02-20 16:35:24.0
The High Density Packaging (HDP) User Group has completed a project evaluating the high frequency loss impacts of a variety of imaged core surface treatments (bond enhancement treatments, including chemical bonding and newer low etch alternative oxides) applied just prior to press lamination. Initial high frequency Dk/Df electrical test results did not show a strong correlation with any of the methods utilized within this project to measured surface roughness. The more significant factor affecting the measured loss is the choice of pre-lamination surface treatment. Most of the new chemical treatment systems outperform the older existing systems which depend upon surface roughness techniques to promote adhesion.
Technical Library | 2015-06-18 12:42:57.0
In the recent past, the Light Emitting Diode (LED) was hailed as the new energy efficient light source that would never have to be replaced. There were claims of 50,000+ hrs lifetime for the humble LED. That story has changed over the last few years as the number and diversity of the LED based products has increased. This is not to say that the original evidence was incorrect, but the initial enthusiastic estimates from the labs did not match the ultimate test, customers. As a result of poor quality products affecting the overall opinion of LED based products, it is critical that manufacturers can be confident in the quality of their product. In current times we want to have products certified, checked and ensure that we have the best quality. For the purposes of this paper we will look at one aspect of LED product, and this is the Lumen maintenance and estimated lifetime. The method described here does not seek to replace using high quality rating labs, but hopefully will allow the manufacturer to know with confidence that their prototype product, upon going to certification labs will be of a high enough quality that no expensive re-designs are required.
Technical Library | 2021-11-03 16:52:47.0
This paper proposes the integration of pulsed photonic sintering into multi-material additive manufacturing processes in order to produce multifunctional components that would be nearly impossible to produce any other way. Pulsed photonic curing uses high power Xenon flash lamps to thermally fuse printed nanomaterials such as conductive metal inks. To determine the feasibility of the proposed integration, three different polymer additive manufacturing materials were exposed to typical flash curing conditions using a Novacentrix Pulseforge 3300 system. FTIR analysis revealed virtually no change in the polymer substrates, thus indicating that the curing energy did not damage the polymer. Next, copper traces were printed on the same substrate, dried, and photonically cured to establish the feasibility of thermally fusing copper metal on the polymer additive manufacturing substrates. Although drying defects were observed, electrical resistivity values ranging from 0.081 to 0.103 Ω/sq. indicated that high temperature and easily oxidized metals can be successfully printed and cured on several commonly used polymer additive manufacturing materials. These results indicate that pulsed photonic curing holds tremendous promise as an enabling technology for next generation multimaterial additive manufacturing processes.
Technical Library | 2020-08-27 01:22:45.0
Initially adopted internal specifications for acceptance of printed circuit boards (PCBs) used for wire bonding was that there were no nodules or scratches allowed on the wirebond pads when inspected under 20X magnification. The nodules and scratches were not defined by measurable dimensions and were considered to be unacceptable if there was any sign of a visual blemish on wire-bondable features. Analysis of the yield at a PCB manufacturer monitored monthly for over two years indicated that the target yield could not be achieved, and the main reasons for yield loss were due to nodules and scratches on the wirebonding pads. The PCB manufacturer attempted to eliminate nodules and scratches. First, a light-scrubbing step was added after electroless copper plating to remove any co-deposited fine particles that acted as a seed for nodules at the time of copper plating. Then, the electrolytic copper plating tank was emptied, fully cleaned, and filtered to eliminate the possibility of co-deposited particles in the electroplating process. Both actions greatly reduced the density of the nodules but did not fully eliminate them. Even though there was only one nodule on any wire-bonding pad, the board was still considered a reject. To reduce scratches on wirebonding pads, the PCB manufacturer utilized foam trays after routing the boards so that they did not make direct contact with other boards. This action significantly reduced the scratches on wire-bonding pads, even though some isolated scratches still appeared from time to time, which caused the boards to be rejected. Even with these significant improvements, the target yield remained unachievable. Another approach was then taken to consider if wire bonding could be successfully performed over nodules and scratches and if there was a dimensional threshold where wire bonding could be successful. A gold ball bonding process called either stand-off-stitch bonding (SSB) or ball-stitch-on-ball bonding (BSOB) was used to determine the effects of nodules and scratches on wire bonds. The dimension of nodules, including height, and the size of scratches, including width, were measured before wire bonding. Wire bonding was then performed directly on various sizes of nodules and scratches on the bonding pad, and the evaluation of wire bonds was conducted using wire pull tests before and after reliability testing. Based on the results of the wire-bonding evaluation, the internal specification for nodules and scratches for wirebondable PCBs was modified to allow nodules and scratches with a certain height and a width limitation compared to initially adopted internal specifications of no nodules and no scratches. Such an approach resulted in improved yield at the PCB manufacturer.
Technical Library | 2021-07-27 14:54:26.0
Fast forward to current time. Today, our society embraces cleanliness. We expect, demand, and evaluate cleanliness in almost every aspect of our lives. We wash our cars and pets. We maintain high cleanliness standards in our hotels and public spaces. We require cleanliness in our restaurants and hospitals. We sanitize our hands throughout the day to prevent illness. We live in a clean-centric culture. While we drive clean cars, stay in clean hotels and eat clean food, there is one part of our life where we actually abandoned cleanliness. Many of the circuit assemblies that affect almost every aspect of our daily lives are no longer required to be clean. Even though our life experience confirms the link between cleanliness and reliability, happiness, health, and safety, circuit assemblies no longer maintain that "cleanliness is next to Godliness" status. This was not always the case. There was a time when virtually all circuit assemblies were cleaned. The removal of flux and other process-related contamination was commonplace. Cleaning was as normal as soldering. As we bring history into current time, one may relate the fall of Rome and its adoption of personal hygiene and the subsequent decline in human health to the large-scale abandonment of cleanliness expectations of circuit assemblies and the subsequent reliability issues it has created. How did this happen? Has history repeated itself?
Technical Library | 2024-07-24 00:51:44.0
A blade server system (BSS) utilizes voltage regulator modules (VRMs), in the form of quad flat no-lead (QFN) devices, to provide power distribution to various components on the system board. Depending on the power requirements of the circuit, these VRMs can be mounted as single devices or banked together. In addition, the power density of the VRM can be high enough to warrant heat dissipation through the use of a heat sink. Typically, at field conditions (FCs), the BSS are powered on and off up to four times per day, with their ambient temperature cycling between 258C and 808C. This cyclical temperature gradient drives inelastic strain in the solder joints due to the coefficient of thermal expansion (CTE) mismatch between the QFN and the circuit card. In addition, the heat sink, coupled with the QFN and the circuit card, can induce additional inelastic solder joint strain, resulting in early solder joint fatigue failure. To understand the effect of the heat sink mounting, a FEM (finite element model of four QFNs mounted to a BSS circuit card was developed. The model was exercised to calculate the maximum strain energy in a critical joint due to cyclic strain, and the results were compared for a QFN with and without a heat sink. It was determined that the presence of the heat sink did contribute to higher strain energy and therefore could lead to earlier joint failure. Although the presence of the heat sink is required, careful design of the mounting should be employed to provide lateral slip, essentially decoupling the heat sink from the QFN joint strain. Details of the modeling and results, along with DIC (digital image correlation) measurements of heat sink lateral slip, are presented.
Technical Library | 2021-07-20 20:02:29.0
During the manufacturing of printed circuit boards (PCBs) for a Flight Project, it was found that a European manufacturer was building its boards to a European standard that had no requirement for copper wrap on the vias. The amount of copper wrap that was measured on coupons from the panel containing the boards of interest was less than the amount specified in IPC-6012 Rev B, Class 3. To help determine the reliability and usability of the boards, three sets of tests and a simulation were run. The test results, along with results of simulation and destructive physical analysis, are presented in this paper. The first experiment involved subjecting coupons from the panels supplied by the European manufacturer to thermal cycling. After 17 000 cycles, the test was stopped with no failures. A second set of accelerated tests involved comparing the thermal fatigue life of test samples made from FR4 and polyimide with varying amounts of copper wrap. Again, the testing did not reveal any failures. The third test involved using interconnect stress test coupons with through-hole vias and blind vias that were subjected to elevated temperatures to accelerate fatigue failures. While there were failures, as expected, the failures were at barrel cracks. In addition to the experiments, this paper also discusses the results of finite-element analysis using simulation software that was used to model plated-through holes under thermal stress using a steady-state analysis, also showing the main failure mode was barrel cracking. The tests show that although copper wrap was sought as a better alternative to butt joints between barrel plating and copper foil layers, manufacturability remains challenging and attempts to meet the requirements often result in features that reduce the reliability of the boards. Experimental and simulation work discussed in this paper indicate that the standard requirements for copper wrap are not contributing to the overall board reliability, although it should be added that a design with a butt joint is going to be a higher risk than a reduced copper wrap design. The study further shows that procurement requirements for wrap plating thickness from Class 3 to Class 2 would pose little risk to reliability (minimum 5 μm/0.197 mil for all via types).Experimental results corroborated by modeling indicate that the stress maxima are internal to the barrels rather than at the wrap location. In fact, the existence of Cu wrap was determined to have no appreciable effect on reliability.
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